PORTLAND, Ore. — True three-dimensional (3D) chips were demonstrated recently at the 2014 International Electron Devices Meeting (IEDM, Dec. 13-17, San Francisco) by Stanford University. Most 3D chips use through-silicon-vias (TSVs) to stack separately manufactured dies, such as the Hybrid Memory Cube, which stacks DRAM die by Micron Technology, Inc., of Boise, Idaho.
A startup -- BeSang Inc. of Beaverton, Ore. -- has licensed its proprietary process to SK Hynix Inc. of Icheon, South Korea, for building true 3D chips without TSVs. But Stanford's demonstration showed that any fab can stack any number of layers of logic and memory atop a standard complementary metal oxide semiconductor (CMOS) die. For the demonstration, Stanford stacked a standard CMOS chip atop two layers of metal-oxide resistive random access memories (RRAM) and a top layer of logic circuitry using carbon-nanotubes as the transistor channel.
3-D chip from Stanford connects four layers with standard vias, with the bottom being standard CMOS, the top carbon-nanotube logic transistors, and the middle two layers of resistive random access memory (RRAM).
(Image: Stanford, Mitra/Wong Lab)
"The key is that if you want extreme levels of energy density efficiency that you can't get using through silicon via (TSVs) it is crucial that you use conventional inter-layer vias," Subhasish Mitra, a Stanford professor of electrical engineering, tells EE Times. "We built these layers one on top of each other using conventional vias with no trouble at all to demonstrate that it was possible."
The method used was to manufacture a standard CMOS logic chip for the bottom, then cover it with a silicon dioxide insulator, and, using an argon sputter etch, to planarize it. The next layer -- RRAM composed of titanium nitride, hafnium oxide (as the active switching layer), and platinum -- was then fabricated atop the CMOS layer at 200 degrees Celsius (so as not to damage the CMOS die) using conventional interlayer vias for interconnect.
Then another layer of insulating silicon dioxide was deposited atop the RRAM and planarized, after which another layer of RRAM was deposited, along with another layer of insulating silicon dioxide. The top layer was then first covered with nanotubes, all lying in the same direction, using a lift-off method from a quartz wafer where they were grown. In order to achieve enough density, the researchers performed this CN transfer method 13 times. Conventional inter-layer vias (ILVs) and lithography techniques were then used to fabricate the carbon nanotubes into the channels of the transistors on the top layer of logic.
"We could use this technique to fabricate any number of layers," professor H.S. Philip Wong tells EETimes. "We used rather relaxed design rules to fabricate the layers at our academic fab, but in other demonstrations we have shown that our process can scale all the way down to modern commercial levels using vias as small as 20 nanometers."
Standard planner CMOS chips (left) put logic and memory on are separate structures connected with by wires or through silicon vias (TSV). Stanford engineers used low-temperature processes to three layers atop the CMOS chip using standard vias for higher density.
(Image: Stanford, Mitra/Wong Lab)
Stanford was also keen to show off its carbon nanotube transistor (CNT) capabilities on a planarized silicon dioxide surface by using standard patterning techniques on its top layer of parallel nanotubes to form them into field-effect transistors (FETs) with about 50 nanotubes per channel. Stanford believes that carbon nanotube transistors will outlive silicon transistors as the technology of the future, because their energy efficiency is 10 times better than silicon.
"What we wanted to show was that you can start with standard silicon CMOS on the bottom, and still build 3D chips, but in the future we expect people to switch to carbon nanotube transistors, because they will extend beyond the roadmap for silicon, which is why we demonstrated real carbon nanotube circuits, not just a test transistors, on the top of the stack."
The team ensured that the CNT layers were fabricated at a temperature low enough so as not to damage the RRAM, and the RRAM was fabricated at a temperature low enough not to damage the CMOS die on the bottom. The CNFETS measured greater than a 5,000 on-to-off ratio. Thousands of regular vias were drilled to interconnect all the layers to making the carbon nanotube field effect transistors (CNFETs) act as the selectors for the RRAM.
Also contributing to the work were Stanford professors Krishna Saraswat and Yoshio Nishi, along with Stanford doctoral candidates Max Shulaker and Tony Wu.
— R. Colin Johnson, Advanced Technology Editor, EE Times