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Toshiba Ups Ante in 3D NAND Fray

3/31/2015 03:37 PM EDT
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Austin Tech Watcher
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design rules on 3D NAND
Austin Tech Watcher   4/7/2015 6:45:22 PM
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Thanks for an excellent article. I did not know that Intel/Micron were using floating gate in 3D NAND, which recalls Intel presentations about how FG was doomed because so few electrons would be used in a single bit, and thus vulnerable to disturbs. My question is about the promise that 3D NAND would use relaxed design rules, and be able to avoid the lithography expense of double and triple patterning. Is it fair to say the equipment cost will only partially shift to deposition and etch, with a net savings due to the lower litho expenses? Thanks again.

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