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10 Views of Semicon West

Roadmap being drawn for chip stacks
7/17/2015 12:45 PM EDT
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docdivakar
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Re: 10 Views of Semicon West
docdivakar   8/13/2015 1:52:52 PM
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Rick, thanks for info which is really useful to those who missed Semicon West 2015.

Qualcomm's Campbell's statement "there's no true transfer of wafer or die knowledge to packaging teams to help them accelerate yield" speaks volumes on why status-quo does need disruption. Chip-package interaction which were hitherto resolved (upto 28nm as he noted) using packaging techniques in a posteriori flow does not work for smaller nodes and thinner chips, whether one stacks them or not. Futhermore, applications in wearables and IoTs will dictate new packaging rules that the Silicon must accommodate in the design stage itself.

MP Divakar

chipmonk0
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Fact Check ?
chipmonk0   7/20/2015 1:07:03 PM
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@ RickMerritt :

the Figure for the AMD stack in your article shows a 5 die stack over a 2.5 d Interposer but it is only computer generated graphics. The adjacent SEM of a x-section of a real die stack (?) shows only a single die attached by microbumps to the Interposer. Perhaps AMD or ASE will like to share with us the x-section of a functioning 3d stack with the no. of die in the stack > 1 !

 

 

Or_Bach
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The Path Forward - Monolithic 3D IC
Or_Bach   7/17/2015 8:09:47 PM
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It is clear that path forward is 3D or as some call - stacking.

And it need to be low cost with rich vertical connectivty with low RC and  => which is also called - monolithic 3D.

And the good news is, that now the 'game changing' technology enable monolithic 3D using existing fab and existing transistor process ! 

resistion
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ASML WPD
resistion   7/17/2015 3:15:45 PM
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ASML EUV wafers/day only increasing 500/year. Still too slow by 2019 (3000 wpd). Recent demos of 7nm node printing show dose is increasing over 20 mJ/cm2 compared to 10nm.

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