Open source processor core gains traction
SAN JOSE, Calif. – RISC-V is on the march as an open source alternative to ARM and Mips. Fifteen sponsors, including a handful of high tech giants, are queuing up to be the first members of its new trade group which will host next week its third workshop for the processor core.
RISC V is the latest evolution of the original RISC core developed more than 25 years ago by Berkeley’s David Patterson and Stanford’s John Hennessey. In August 2014, Patterson and colleagues launched an open source effort around the core as an enabler for a new class of processors and SoCs with small teams and volumes that can’t afford licensed cores or get the attention of their vendors.
Google, Hewlett Packard Enterprise (HPE), Lattice, Microsemi and Oracle – which is hosting next week’s workshop -- will be among the first members of RISC-V. Tool vendor Bluespec also is joining the group.
The group is still drafting the details of the open source license which will be part of its member agreement. The terms will specify a zero-royalty RAND license as well as verification suites licensees must run to use the RISC-V logo.
Users will need to contribute as open source any changes they make to the core. Nevertheless, “there’s plenty of room for secret sauce and company-specific implementations,” said Rick O'Connor, executive director of the RISC-V Foundation.
Currently RISC-V runs Linux and NetBSD, but not Android, Windows or any major embedded RTOSes. Support for other operating systems is expected in 2016.
So far, a camera SoC is the only shipping chip said to use the open source core commercially. A handful of university projects use the core including a government-supported effort at IIT Madras in India to develop a homegrown processor family. The IIT chips and three or four other processors in the works use the Rapid IO interconnect as a front-side bus, said O'Connor who also manages the Rapid IO trade group.
At the workshop, two talks will describe boot environments for RISC-V in separate papers presented by engineers from Google and a team from HPE and Intel. A representative of military contractor BAE Systems will talk about building the software ecosystem for RISC-V.
Next page: FPGA accelerators tap RISC-V
FPGA accelerators tap RISC-V
Three papers will describe FPGA-based accelerators using embedded RISC-V cores, a hot area given work by Web giants such as Microsoft and Baidu on FPGA accelerators.
Jan Gray, a former software architect on a Microsoft parallel computer, will describe an FPGA accelerator using RISC-V cores. Guy Lemieux, an academic and chief executive of VectorBlox Computing, will describe a similar project.
ROA Logic, an FPGA and ASIC design services company in the Netherlands, will describe various RISC-V implementations.
“I was surprised by how many people are getting involved -- we’ll be sold out with about 130 people,” said O’Connor. “You’ll see folks developing products that cover the waterfront from embedded to high-end server-class processors -- initial [commercial] products will be lower-end embedded SoCs,” he added.
The RISC-V instruction set supports 32- and 64-bit designs as well as vector and out-of-order extensions.
Even if it gains significant traction, RISC-V is not likely to have any major impact on ARM and Mips, given those vendors are well established with broad sets of customers and partners. However, the architecture could enable a new class of designs from small teams that would otherwise lack the heft to design their own chips.
"Open source has worked well in the software community, so there’s a place for this type of effort in CPUs but there’s a lot of practical issues they have to overcome, and I wouldn’t see this competing with ARM anytime soon,” said Linley Gwennap, principal analyst of the Linley Group (Mountian View, Calif.).
The lack of support is the biggest challenge ahead for anyone adopting RISC-V. “Open source software spawned business models for providing support, and that’s probably what will have to happen here,” Gwennap added.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times