RPARIS—Researchers from the University of Wisconsin Madison have leveraged the high carrier mobility of flexible silicon nanomembranes (NM) with the scalability of nanoimprinting lithography (NIL) to produce thin-film flexible RF transistors capable of operating at 38GHz.
According to their simulations, their manufacturing strategy could yield 100 GHz-capable thin flexible RF transistors to be manufactured at low cost and low temperature on large rolls of PET.
Their paper "Fast Flexible Transistors with a Nanotrench Structure" published in the journal Scientific Reports details how they overcome the limitations of conventional lithography.
Rather than try to dope selectively a silicon substrate to pattern transistors, the researchers indiscriminately doped a whole silicon nanomembrane (created from a silicon-on-insulator (SOI) wafer, hence keeping the superior charge carrier mobility of bulk silicon versus typically low-mobility organic materials.
They then used electron-beam lithography to carve out a nano-imprinting mold which they use to imprint an etching mask pattern through a photoresist layer, subsequently used to etch a deep nano trench in the Si NM (100nm wide by 250nm deep). After depositing source and drain electrodes and undercutting the buried oxide to release the Si NM, the active nanomembrane is flip transferred onto an adhesive coated PET substrate. Further dry etching defines the perimeter of the active region, then an Al2O3 gate dielectric and gold gate electrodes are deposited above the 100nm trench to finalise the transistor — see Figure 1.
Fig. 1: Comparison of the device structures (cross-sectional view) and fabrication processes between (a) 3-D nano trench Si NM flexible RF TFTs, and (b) conventional 2-D TFTs. The effective channel lengths Lch are marked in red in (a3,b3). The smallest Lch of the nano trench TFT can reach down to 50 nm via NIL and that of the conventional TFT can only reach down to about 1.5 μm. (a1) Blanket phosphorous ion implantation and thermal anneal. (a2) Nano trench formation via nanoimprint. (a3) Final structure of nano trench TFT where the channel length Lch is defined by nanoimprint. (b1) Photolithography to define S/D regions for ion implantation. (b2) Selective ion implantation and thermal anneal. (b3) Final structure of conventional TFT where the channel length Lch is limited by gate electrode and dopant out-diffusion during ion implantation and thermal anneal. Source University of Wisconsin Madison.
Remarkably, all of the device fabrication processes were carried out at temperatures lower than 150°C (except for the first doping and recrystallization steps performed in a blanket fashion before releasing the Si NM from SOI).
Fig. 2: Schematic illustration (left column), cross section structure (middle column), and corresponding microscopic images (right column) of nano trench Si NM flexible RF TFTs. (a) Defining a nano trench on a phosphorus implanted p− SOI substrate using NIL. (b) Dry etching to separate the n+ area in order to form a path of n+/p−/n+ from source to drain. (c) A partially completed TFT after undercutting the buried oxide to release the Si NM, which forms the active region, and forming the source and drain contacts. (d) Flip transfer of the Si NM with the source and drain electrodes onto an adhesive coated PET substrate. (e) Dry etching to define the perimeter of the active region. (f) Deposition of an Al2O3 gate dielectric layers and gold gate electrodes above the trench. (g) Optical image of arrays of the bent TFTs on a PET substrate. Source University of Wisconsin Madison.
With a unique, three-dimensional current-flow pattern, the high performance transistor consumes less energy and operates more efficiently. And because the researchers’ method enables them to etch much narrower trenches than conventional fabrication processes would allow them on silicon nanomembranes (notoriously difficult to process due to the diffraction of exposed light on the plastic substrate and the substrate's thermal plasticity), it also could enable semiconductor manufacturers to pack more transistors on flexible sheets, re-using the mold in a roll-to-roll manufacturing process for the mass fabrication of flexible electronics.
To put things in perspective, the smallest channel length of flexible transistors made on plastic substrates using the semiconductor nanomembranes is about 1 μm, report the researchers, an order of magnitude larger than their proposed design.
Visit the University of Wisconsin Madison at www.wisc.edu
Access the full paper at http://www.nature.com/articles/srep24771
Article originally posted on EE Times Europe.