SAN FRANCISCO—Leti, a CEA Institute, came to Semicon West here this week to unveil its second generation 3D Network-on-Chip (3D-NoC) technology.
Using the new 3D-NoC technology, Leti researchers have developed an on-chip communications system that it says substantially boosts computing performance while reducing energy consumption. Leti researchers accomplished this by stacking chips in a single enclosure, or by placing the chips side by side on a silicon interposer.
Asked about the new 3D-NoC technology’s demonstrator, Olivier Faynot, microelectronic component section manager at Leti’s Silicon Component Div., told us, “Its layout is done, it’s now in foundry.” Once chips are fabricated at a foundry, they will be assembled at Leti, he said. “We will get silicon out in the fourth quarter of this year.”
Quest for 3D ICs
The chip industry’s quest for 3D ICs has come a long way in the advance of 3D integration technology. Successful examples of 3D ICs today include imagers, 2.5D interposers and 3D memory cubes.
Leti has been also pursuing the development of advanced 3D technology bricks (TSVs, μ-bumps, hybrid bonding, etc.), and designing advanced 3D circuits as pioneer prototypes.
The French research institute disclosed its first version of 3D NoC demonstrator in a paper submitted to ISSCC earlier this year.
In that paper, Leti researchers presented a homogeneous 3D circuit composed of regular tiles assembled using a 4×4×2 network-on-chip, using robust and fault tolerant asynchronous 3D links. The demonstrator provided 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.
The second version of Let’s 3D-Noc technology, unveiled this week, is called INTACT (which means “ACTive INTerposer.”)
The new 3D circuit combines a series of chiplets fabricated at the FDSOI 28nm node and co-integrated on a 65nm CMOS interposer. The active interposer integrates several lower-cost functions, such as communication through the NoC and system I/Os, power conversion, design for testability and integrated passive components, according to Leti’s announcement.
Leti’s latest 3D IC project demonstrated that with 3D technologies and through silicon vias (TSV), it’s possible to stack various dies together. This development “opens a full scope of new application possibilities,” said Faynot. In short, you can integrate more devices from potentially different technologies (CMOS, MEMS, DRAMs, etc.), he explained.
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