BeSang wants to lower barrier to 3D NAND flash LAKE WALES, Fla—The inventor of 3D monolithic chip technology back in 2010, BeSang Inc. (Beaverton, Ore.), claims to have since created a superior three-dimensional (3D) architecture for NAND flash. Frustrated with licensee Hynix's slow implementation of its monolithic 3D technology, BeSang is opening the door to partnerships with other memory houses, as well as offering to contract-fab the chips for resale by others, at a price that reduces the cost-per-bit of 3D NAND from over 20¢ to about 2¢ per gigabyte.
Problems with conventional 3D NAND are discussed including cell size, vertical scaling limitation, inefficiency of product architecture, and how BeSang aims to remedy them.
"Samsung’s most advanced 3D NAND stacks up to 48 layers of memory cells in the vertical direction. Therefore, we would expect that 48-layer 3D NAND should be cheaper than planar NAND. Ironically, 3D NAND is still expensive compared to planar NAND," said Sang-Yun Lee, chief executive officer (CEO) of BeSang. "Their fundamental problem is the gigantic cell size of their 3D NAND."
SanDisk's 48-layer 3-D NAND costs more per bit than 2-D NAND according to ForewardInsights.
The cell size of 3D NAND is about 10X bigger (31,000 square nanometers) than planar 2-D NAND due to the use of over 60 percent of its area for control logic (34 percent), a tungsten isolation slit (20 percent) and a word-line staircase (26 percent).
BeSang's claim to fame since its inception, has been its ability to build 3D chip monolithically with all control logic on the bottom layer, leaving the entire top area for vertical memory cells (both of which can be stacked). Competitive 3D NAND bit cells use up to 31,000 square nanometers per bit, due to using about 60 percent of the cell for three functions: control logic (34 percent), a tungsten isolation slit (20 percent) and a word-line staircase (26 percent). On the other hand, BeSang's monolithic process can fit 30 NAND bits into the same area, according to the company, thus accounting for their cheaper price-per-bit.
Besides bigger cells, 3D NAND from Samsung and others use a difficult to implement staircase word-line architecture that extends about 20 microns for Samsung's 32-layer 3-D NAND or 40 microns for its proposed 64-layer 3D NAND, according to BeSang. The result is not only lower bits per square micron, but also longer wafer processing time due to the multiple staircase etching and contact forming steps.
BeSang claims its tiny normal-sized vias can pack millions of interconnects per 3-D chip layer resulting in a lower cost-per-bit than Samsung's 32-, 48- or 64-layer 3-D NAND.
"With just five masks, we can process our 3D NAND with three-times the capacity of SanDisk's or Samsung's designs in just five days processing, whereas it takes them as much as 10 weeks to process their 3D NAND chips," said Lee. "The capital equipment we need also costs as much as 10-times less than theirs."
BeSang 3-D chips locate their interconnection, selection and read-write logic on the bottom and its vertically stacked NAND cells tightly packed on the top.
In addition to licensing its technology to memory makers, BeSang is also offering turnkey delivery of what it calls its 3D Super-NAND to customers who wish to resale them in the commercial market ($30 million minimum order). Both 15-nanometer and 20-nanometer versions are being offered (to be built in a foundry of BeSang's choice). The company is also promising a single-chip 1-terabyte 3D Super-NAND design within two years.
In the space that traditional 3-D NAND fits a single cell, BeSang claim to be able to fit up to 50 cells, thus its beats by 3X a 48-layer Sansung single cell (left) with 150 cells for a five-layer BeSang 3-D NAND (right).
— R. Colin Johnson, Advanced Technology Editor, EE Times