CUPERTINO, Calif. — IBM’s Power 9 processor, described for the first time at Hot Chips yesterday, could become a break out chip, seeding new OEM and accelerator partners and rejuvenating Big Blue’s bid against archrival Intel in high-end servers.
The 14nm Power 9, first mentioned in March, takes a bold if somewhat fragmented strategy in the hot area of accelerators. It is IBM’s first Power chip to emerge as a family to enable a range of scale up and scale out system designs.
Like past IBM microprocessors, to reach new performance levels it uses a gob of memory—including a whopping 120 Mbyte embedded DRAM in shared L3 cache riding a 7 Tbit/second on-chip fabric.
Across a range of benchmarks, Power 9 should deliver from 50% to more than twice the performance of the Power 8 when the new chip arrives late next year, said Brian Thompto, a lead architect for the chip. New core and chip-level designs contribute to the performance boost.
IBM will release four versions of Power 9 (shown above). Two will use eight threads per core and 12 cores per chip geared for IBM’s Power virtualization environment; two will use four threads per core and 24 cores/chip targeting Linux. Both will come in two versions — one for two socket servers and 8 DDR4 ports and another for multiple chips per server with buffered DIMMs.
The diversity of choices could help attract OEMs. IBM has been trying to encourage others to build Power systems through its OpenPower group that now sports more than 200 members. So far, it’s gaining most interest from China where one partner is making its own Power chips.
Use of standard DDR4 DIMMs on some parts will lower barriers for OEMs by enabling commodity packaging and thus lower costs.
Power9's 120 MByte L3 is parsed out in 10 MByte blocks shared by two cores.
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