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Transistor Trick Beats Moore

Cheaper Chip Nodes Improved
9/14/2016 00:01 AM EDT
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ywidjaja
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Re: substrate current
ywidjaja   9/29/2016 1:14:54 PM
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Thank you for the clarification.

The booster current (to source region) is low and is not what contributes to the transistor current gain (at least, not directly). The transitor current gain comes from the amplification of booster current by lateral BJT (source - base - drain). In addition, this booster current only flows in the logic-high state. 

-Yuniarto (Zeno)

resistion
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Re: substrate current
resistion   9/28/2016 12:40:40 AM
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Substrate current would be the current from the booster to source or drain.

ywidjaja
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Re: substrate current
ywidjaja   9/27/2016 2:06:24 PM
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Could you elaborate what you mean by substrate current?

The substrate is contacted through the usual substrate contact. 

-Yuniarto (Zeno)

R_Colin_Johnson
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Re: substrate current
R_Colin_Johnson   9/27/2016 11:53:19 AM
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They did not mention a fourth buried electrode, but I see what you mean. Otherwise they would have to change the state of the whole chip. Perhaps that detail would be a part of the specific application being implemented?

resistion
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substrate current
resistion   9/27/2016 11:40:53 AM
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Seems risky to play around with substrate current, unless they have a buried fourth terminal.

R_Colin_Johnson
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Re: Making 28 nm better than 7nm !!!
R_Colin_Johnson   9/26/2016 1:25:10 PM
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Yes, Moore's Scaling Law is dead, the future will be dominated by More-than-Moore architectural and material innovations like this one.

Or_Bach
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Making 28 nm better than 7nm !!!
Or_Bach   9/26/2016 12:41:19 PM
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The boosted transistor invented by Zeno provides 4x improvement on power-delay product ! (By adding Bi-Polar vertical enhancement to the planner CMOS)

The traditional scaling these days provides 1.3x per node.

=>  5 nodes equivalence, making 28 nm better than 7nm !!!

And it is electrically tunable, without the need for SOI. 

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