Advertisement
REGISTER | LOGIN
Breaking News
News & Analysis

TSMC, GF/Samsung Battle at 7nm

Intel may take back seat to foundries
10/21/2016 01:09 PM EDT
53 comments
NO RATINGS
Page 1 / 2 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 6   >   >>
witeken
User Rank
Freelancer
Re: I Already Covered this with Density Comparisons
witeken   12/12/2016 11:26:32 PM
NO RATINGS
We now know that TSMC will use 40nm, but with SAQP, not SADP, which falsifies your analysis.

resistion
User Rank
Author
Tricky phrase in IEDM 2016 abstract
resistion   12/4/2016 1:54:22 PM
NO RATINGS
"Here, EUV lithography AND other advanced patterning approaches have led to the tightest contacted polysilicon pitch (44/48nm) and metallization pitch (36nm) ever reported for FinFETs." Looks like it's not conventional EUV patterning. Can just as well substitute "immersion" for "EUV".

resistion
User Rank
Author
Re: People love the future waaaay too much
resistion   11/16/2016 8:20:22 AM
NO RATINGS
We now know that Samsung, TSMC and Intel are all now huddled around the 1D SADP limit, ~19 nm hp. Samsung just recently got there:

https://news.samsung.com/global/samsung-expands-its-advanced-foundry-offerings-with-14lpu-and-10lpu-processes

michgan0
User Rank
Author
Re: Yuwegedusitesnaszemedia
michgan0   10/31/2016 2:17:42 PM
NO RATINGS
Sang Kim

 I would like to comment especially on speed signaling quated here,  the GF/Samsung 7nm process will use "dual-straind channels on a thick strain-relaxed buffer virtual substrate to combine tensil-strained NMOS and compressively strained SIGe PMOS for enhancement of drive current by 11% and 20%, respectively," its abstract said.

The uniqueness of 7nm is that 7nm at the bottom and 4nm at the top is so narrow that the entire channel is fully inverted as seen in a double gate transistor, resulting in large drive currents. Therefore, implementation of III-V or Ge channel is unnecessary or even detrimental because it dose not provide higher transistor drive currents than the fully inverted channel that I talk about here.

aeassa
User Rank
Author
Re: Yuwegedusitesnaszemedia
aeassa   10/28/2016 12:26:04 PM
NO RATINGS
Can you say which technology (TSMC 7nm or Intel 10nm) has the density edge as given by the product of MMP and CPP without going into specific numbers?

resistion
User Rank
Author
Re: Yuwegedusitesnaszemedia
resistion   10/26/2016 8:31:28 AM
NO RATINGS
Ok, thanks. I had the (apparently wrong) impression that TSMC 10nm was already close to Samsung 10nm. There were no official revelations of course, just some web speculations, and also my assumption that Samsung and TSMC 10nm were somewhat comparable in gross design rules.

IJD
User Rank
Author
Re: Yuwegedusitesnaszemedia
IJD   10/26/2016 8:08:38 AM
NO RATINGS
Intel 10nm and TSMC 7nm look very similar (both at the usable SADP limit), TSMC 10nm is considerably less dense with bigger CPP and MMP.

resistion
User Rank
Author
Re: Yuwegedusitesnaszemedia
resistion   10/26/2016 7:52:59 AM
NO RATINGS
I mean also TSMC's own 10nm.

IJD
User Rank
Author
Re: Yuwegedusitesnaszemedia
IJD   10/26/2016 7:28:01 AM
NO RATINGS
I assume you mean Intel's 10nm?

(and to give Intel credit, their "10nm" is close to 10nm according to ASML's formula -- just like TSMC's very similar "7nm"...)

resistion
User Rank
Author
Re: Yuwegedusitesnaszemedia
resistion   10/26/2016 7:04:08 AM
NO RATINGS
Looks like tsmc 7nm MMP is same as 10nm, or at least very close.

Page 1 / 6   >   >>
Most Recent Comments
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed