SAN JOSE, Calif. — TSMC will go head-to-head with the partnership of IBM, Globalfoundries and Samsung to publicly detail rival 7nm processes at a technical conference in December. The trio’s process will use extreme ultraviolet lithography to achieve impressive gains, but TSMC likely will get to market first due to challenges getting EUV into production.
Using EUV, GF and Samsung claim they will deliver “the tightest contacted polysilicon pitch (44/48nm) and metallization pitch (36nm) ever reported for FinFETs,” in an abstract for the International Electron Devices Meeting (IEDM).
The pitches leapfrog the 56nm gate pitch Intel announced in August for its 10nm process, claiming industry-leading density for the node it aims to have in production next year. Observers have started to suggest both TSMC and Samsung might leapfrog Intel which has slowed the pace of releasing new process technologies as progress in Moore’s law becomes more complex and costly.
For its part, TSMC will describe at IEDM a 0.027µm2 SRAM test cell made in its 7nm process using immersion steppers. The 256-Mbit, six-transistor SRAM has the smallest cell size reported to date, TSMC claimed, and sports “full read/write functionality down to 0.5V,” it added.
The abstract echoed claims for the 7nm node that TSMC first made at an event here in September. The process will deliver “more than three times the gate density and either a speed gain (35-40%) or power reduction (>65%) versus the company’s commercial 16nm FinFET process,” the abstract said.
“IEDM is clearly the coming out party for 7nm,” said G. Dan Hutcheson, president of VLSI Research. “The key message is Moore’s law is not stopping because customers are moving to 7nm," he said.
On Monday when Samsung announced its 10nm process, it said it would skip a version of 7nm using today’s immersion lithography. Instead it said it will roll out 7nm with EUV targeting production before the end of 2018. For its part, TSMC said it will have at least limited production in 2017 for its 7nm process with immersion steppers.
The net result is in the course of 18 months chip designers will see at least three variants of 7nm -- separate immersion variants from TSMC and Globalfoundries and the EUV version from GF/Samsung. Intel has yet to detail its 7nm node, but said it expects density to rise and cost per transistor to fall.
To speed signaling, the GF/Samsung 7nm process will use “dual-strained channels on a thick strain-relaxed buffer virtual substrate to combine tensile-strained NMOS and compressively strained SiGe PMOS for enhancement of drive current by 11% and 20%, respectively,” its abstract said. The approach uses a “novel trench epitaxy to minimize the resistance of the highly scaled contact regions,” it added.
In September, GF said it developed its own 7nm process using immersion steppers that will be in production in 2018. It did not mention it was still collaborating with Samsung on the EUV version. The 7nm immersion process will have a logic density of 17 million gates/mm2, a spokeswoman said.
The TSMC 7nm process uses “a raised source/drain epitaxial process that strains the transistor channel and reduces parasitics, a novel contact process, and a copper/low-k interconnect scheme featuring different metal pitches and stacks,” the abstract said.
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