The TII approach (a) deposits thin-oxide and hard-mask (HM) layers and uses lithography to print features in the HM. Then (b) argon ions are implanted at opposing angles. Damaged parts of the oxide layer are etched away, and the HM is removed (c, d). The patterned oxide layer is then used as an HM to pattern the underlying IC layer, after which the oxide is removed (e,f).
Given that TII uses “fairly standard CMOS processes … I’m pretty sure some fabs have tried it — this is very easy compared to SADP — but they won’t say anything until they put it in high-volume manufacturing because this industry is so competitive,” he said.
Any adopters would have to license the patent-pending technique through the Berkeley technology transfer office, he added.
As a follow-on, researchers are exploring how to use the technique to pattern tiny holes. They also are exploring how it could be used to help relax the tight design rules currently required using SADP at 16-nm nodes and beyond. In addition, they continue to experiment with new materials.
The paper had two noteworthy co-authors — Leonard Rubin, the chief device scientist at Axcelis and Tsu-Jae King Liu, a Berkeley vice provost and co-inventor of both the FinFET and SADP. For his part, Peng Zheng recently graduated from Berkeley with his PhD and accepted a job at Intel.
“It’s definitely impressive work,” said G. Dan Hutcheson, chief executive of market watcher VLSI Research.
However, Hutcheson noted several business issues that could stand in the way of adopting the technique.
“Cost improvement, while impressive on paper, is seldom enough to get companies to switch — just look at SOI,” said Hutcheson, pointing to the long road to market that silicon-on-insulator has traveled.
In addition, “there are lots of unanswered risk questions, like yield and damage to underlying layers,” he said, adding that chip makers are “typically very conservative when it comes implant.”
— Rick Merritt, Silicon Valley Bureau Chief, EE Times