SANTA CLARA, Calif. — Trying to cover the waterfront, TSMC disclosed plans for new high-, mid- and low-end processes at an annual event here. They included an enhanced 7nm FinFET node using extreme ultraviolet lithography, a 12nm upgrade of its 16nm process and a 22nm planar technology — its answer to fully depleted silicon-on-insulator (FD-SOI).
The foundry also described enhancements to its two chip-stacking techniques, advances in RF CMOS and work in transistors and materials, paving the way to a 3nm node and beyond. In addition, it previewed design capabilities using machine learning that it will offer before the end of the year.
Among its achievements, TSMC noted 76 percent yields on the 256Mbit SRAM made in its first-generation 7nm node, which will be in volume production next year. It also reported that an ARM Cortex-A72 processor in the node exceeded 4GHz using a new design flow.
The proliferation of different nodes, sub-nodes and platforms threatens to create a dizzying array of options. TSMC has clearly focused on easing migrations for designers, sometimes at the expense of advances measured in single digits.
The Taiwan company, already the world’s largest foundry by far, expects to ship 11 million 12-inch-equivalent wafers this year, a typical 10 percent annual increase. The biggest share—two million wafers—will use its planar 28nm processes for which it is boosting capacity 15 percent this year.
TSMC has taped out nearly 800 chips using flavors of its 28nm process. It has shipped 4.5 million 28nm wafers to date, clearly a big sweet spot it aims to defend.
Globalfoundries hopes to capture many of those customers starting this year with 22nm FD-SOI, a lower cost, lower power alternative with similar performance to TSMC’s 16nm FinFET node. TSMC claims its 22nm process provides an easier migration path from 28nm while FD-SOI requires redesigned intellectual property cores.
“Bulk semiconductor technology has been enhanced for 30 years and is used by Intel and Samsung,” the world’s two largest chip makers, said Mark Liu, TSMC’s co-chief executive in a brief interview after a keynote here. “FD-SOI will always be the technology of the future,” he quipped.
The news comes the same day NXP announced it will use FD-SOI for multiple future processors. So far, a total of just 10,000 FD-SOI wafers/month are shipping from all fabs including Globalfoundries and STMicroelectronics, said Sam Wang, a chip analyst for Gartner.
Globalfoundries may be slightly ahead in timing, ramping its 22nm FD-SOI process now with Sony image sensors in production. TSMC said its 22nm process will be in production next year, aimed at 5G RF and other mobile chips including image processors and components for wearables and the Internet of Things.
The 22nm FD-SOI node sports similar specs to TSMC’s 22nm process, “but it does not have the comprehensive IP ecosystem… and the manufacturing track record we have,” said B.J. Woo, vice president of business development at TSMC.
TSMC also plans an ultra-low power version of its 12nm FinFET process, supporting 0.5V operation and starting risk production before June. It will likely be positioned as a competitor to the 12nm FD-SOI process Globalfoundries announced last year but is not expected in production until 2019.
The ultra-low power TSMC 22nm process should deliver a 20 percent area shrink and either 0.45x the power or 1.32x the speed of its 28 HPM process, Woo said. Compared to its 28 HPC+ process, the 22nm is a direct optical shrink with better transistors and 0.6 Vdd operation offering 10 percent smaller size and 35 percent less power or 15 percent more speed, she said.
TSMC’s 22nm node uses the same mask counts, design rules, SRAM bit cells and I/O devices as its 28HPC+ node. Designers only need to adopt its boosted transistors and re-characterize foundation IP to ensure they meet new margins, Woo said.
“The migration effort is really different [from FD-SOI]—it’s a day and night difference,” said Jack Sun, a vice president of R&D at TSMC.
TSMC’s Liu said the foundry expects 70 tape outs of IoT chips this year across its family of ultra-low power processes that range from 55 to 28nm. The 40nm ULP process has been characterized for near-threshold operation driving energy efficiency to 11 microamps/MHz, he said.
Next page: EUV rolls into 7+nm node in 2018
EUV rolls into 7+nm node in 2018
TSMC’s plans to use EUV on an enhanced version of its 7nm process was perhaps the biggest eye opener of the event.
The foundry achieved similar yields using immersion and EUV steppers on a 7nm test chip. In addition, it hit 125W with its ASML 3350 EUV system, providing confidence it can hit about 250W for high volume manufacturing with EUV in 2019 on a 7+nm process.
Samsung announced late last year it plans to use EUV in a 7nm process that could be in production by 2019. “We believe we will be the first one” to use EUV in volume production, said TSMC’s Woo with risk production starting by June 2018.
The company did not detail exactly how it will use EUV steppers except to say it will be at multiple layers. Woo showed a demonstration of EUV 1P1E lines and spaces replacing 4P4E for immersion with “comparable yields and electric performance.”
“It’s important to be at least cost neutral [with EUV], you don’t have to wait for the ultimate goal,” said TSMC’s Sun.
The foundry reported throughput between 1,458 and 1,633 wafers/day over three days with its ASML 3350 system. It aims to start risk production with the ASML 3400 stepper announced earlier this month, ramping to volume production in 2019.
TSMC used an unnamed “novel resist” chemical to replace five immersion masks with one EUV mask at pitches ranging from 26-30nm. Liu said the company currently expects EUV could compress as many as 16 immersion masks to four or five.
The enhanced 7nm process, in part, serves the needs of companies such as Apple that demand enhancements for each annual smartphone generation. The 7+ process promises 1.2x greater logic density and 10 percent more speed or 15 percent less power than TSMC’s first-gen 7nm node
To migrate to the 7nm enhancement, designers “just need to comply with new EUV design rules,” Woo said. SRAM, analog and I/O components only need to be re-characterized, she added.
Next page: First generation 7nm starts its ramp
First generation 7nm starts its ramp
TSMC will start risk production on its first-generation 7nm process next month. It expects in May the first of 12 tapeouts in the process this year, and a total of about 20 tapeouts in the first 12 months.
The process should deliver 3.3x greater routed gate density and either 35 percent more speed or 60 percent less power than the foundry’s 16FF+ node. The process includes new cell libraries, cache macros and serdes.
The foundry is developing unique flavors of its processes tailored to the separate needs of automotive, smartphone, high-performance computing (HPC) and IoT markets.
The 7nm HPC platform includes a new design flow being released in June as well as enhanced IP and process optimizations. It drove an ARM A72 to more than 4 GHz. The platform also supports on-chip magnetic inductors to create integrated voltage regulators.
The HPC platform includes high performance transistors that deliver a five percent speed gain over the vanilla 7nm process. Interestingly, TSMC described several techniques driving advances of 4-5 percent across various processes, suggesting the foundry is squeezing out gains wherever it can find them. An automotive variant of the 7nm process will be ready next year.
Just how little volume TSMC is getting at its advanced process nodes is not clear.
One TSMC executive said the foundry expects a steep ramp for its 10nm node to 400,000 total wafers this year. He forecast TSMC will make three times as many 10 and 7nm wafers total in 2019. Another executive said volumes of 10nm wafers will surpass 16nm wafers this year.
The 10nm node is expected to be a short lived one, created in large part for Apple’s iPhone 8. It sports twice the gate density, and either 10 percent higher speed or 25 percent less power than the 16nm node, TSMC said.
TSMC had little to say about either its 10nm or 5nm nodes except ramping 10nm was a primary focus of this year and 5nm will be in volume production in 2020. Previously TSMC suggested it would start use of EUV at 5nm.
Next page: Advances push into 3nm, machine learning
Advances push into 3nm, machine learning
TSMC plans a six-track 12nm FinFET process that falls between its 22nm planar and 10/7nm FinFET nodes. It sees it as an upgrade for midrange mobile and video processors and high-end IoT devices now using its 16FFC process. High end GPUs and FPGA are using a 16FF+ variant and will migrate to 10/7nm.
The 16FFC process which has had eight design wins is not yet in volume production. The 12FFC process should start risk production before June and deliver 1.1x the speed or 0.7x the power of 16FFC process.
Compared to 16FFC, 12nm chips running at less than 2.4 GHz could see 20 percent area shrinks. Those running faster than 2.4 GHz could be optimized for an additional six percent in speed gains.
The 12nm process uses the same design rules, masking layers, SRAM cell layouts, voltage ranges and I/O devices as 16FFC. Like the 22nm process, designers can mainly re-characterize SRAM, analog and I/O components from the prior node.
An ultra-low power version of 12FFC will support 0.5V operation.
Separately, TSMC described RF variants of processes ranging from 28nm to 12nm. They aim to serve a wide range of products including 5G radios operating in millimeter bands. It positioned a 22nm ULP variant against 22nm FD-SOI.
In packaging, TSMC is developing multiple versions of its InFO process, one for HPC supporting substrates as large as 65mm2. An upgrade of TSMC’s 2.5D CoWoS process will support stacks of as many as eight DRAMs using HBM2 on substrates up to 1500mm2.
Meanwhile in its R&D labs, TSMC has built next-generation transistors out of horizontally stack gate-all-around nanowires. It has also demonstrated the structures using germanium. The company also mentioned work in new interconnects and a back-end capping process, all aimed at enabling nodes at and beyond 3nm.
Finally, TSMC will deliver late this year a machine-learning capability for limited functions on ARM A72 and A73 cores. The capabilities include predicting optimal cell clock-gating to bolster overall chip speeds 50-150 MHz.
The techniques use training models maintained by TSMC using open source algorithms such as Caffe. Designers will be able to create custom scripts they keep privately. Ultimately the service will span more processor types and functions.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times