Distant hope for a 14-angstrom node
ANTWERP, Belgium — The semiconductor road map that An Steegen is showing this year has a new node in the upper right hand corner — 14 Å. The placeholder for a 14-angstrom process — a 0.7x shrink from a 2-nm node in 2025 — is a sign of the unflagging optimism of the veteran process technology expert at the Imec research institute.
“We’re still trying to come up with what goes into that bucket, but how we fill it in may be quite different than what we have done before,” said Steegen in an interview at the annual Imec Technology Forum here.
A 14-Å node suggests the atomic limits ahead. A single arsenic atom, one of the larger elements used in semiconductors, measures about 1.2 Å.
As they approach a 14-angstrom future, engineers may start to mix on the same die FinFETs with nanowires or event tunnel FETs or spin-wave transistors. They will certainly start to experiment with more types of memories, and they may be building chips for new kinds of non-Von Neumann computers.
In the near-term, Steegen sees extreme ultraviolet lithography (EUV) being adopted at 7 nm, FinFETs living on to 5- and even 3-nm nodes, and nanowire transistors emerging somewhere along the way.
For now, a 14-angstrom node is just a Powerpoint hope. Click to enlarge. (Images: Imec)
“The confidence level is getting higher and higher from people who work with the hardware” that EUV will be ready for commercial use by early 2020, said Steegen. “Having worked on it for some many years, you see when things are stabilizing.”
Imec was among the first to install prototype EUV systems. It continues to work on one today in its research fab next to a university campus in nearby Leuven.
Steegen expects that EUV “will be sprinkled into process flows at the most critical levels” to make vias and blocks where line ends meet. The work can take three or four passes with today’s immersion steppers, but with its finer resolution, EUV can do it in one.
Engineers working on such advanced nodes will need to check that their designs can be used with either immersion or EUV systems. Those pushing their chips to the reticle limit will use EUV to shrink their designs a bit more.
Despite the small opening, triple and even quad immersion patterning may still be needed to make features with less than a 40-nm pitch. Engineers should not expect design rules to get any simpler anytime soon.
Next page: Choosing resists and transistors
Imec mapped out the power performance future nodes may deliver. Click to enlarge.
Choosing resists and transistors
Finding the right resist materials is one of the last big challenges for getting EUV into production. So far, researchers only get edges smooth if they use EUV exposures above a 20-millijoule/cm2 target.
A handful of companies, including ASML, Tokyo Electron, and ASM, are developing proprietary — read: expensive — techniques to resolve the issues. They generally involve resist treatments and process steps to etch or anneal away roughness.
“The smoothing techniques look very promising, so we feel confident that we can fix line-edge roughness,” said Steegen.
Separately, Imec is developing a pellicle to protect EUV wafers from contamination. It uses carbon nanotubes to provide the strength needed to withstand EUV exposures above 200 W while not preventing most of the light to travel through to the wafer.
Beyond EUV, the next big hurdle is a transition in the design of the basic transistor, the electric switch at the heart of any device. “How long FinFETs scale is a key question that needs to be resolved,” said Steegen.
So far, research indicates that FinFETs can be used at 5 nm, and if all goes well with EUV, maybe even at a 3-nm node. “At the 3-nm node, FinFETs and nanowires perform almost equally well, but nanowire gate pitches offer more scaling,” said Steegen, showing research on a stack of eight nanowires.
Next page: On track scaling and memories
A detailed look at resist issues shows efforts with versions that use chemical assistance and those that donít (CAR and NCAR). LWR/LCDU refers to measures of line-edge roughness that should be no more than a tenth of the feature pitch size, in this chart a range of 3.2 to 2.6. Click to enlarge.
On track scaling and memories
If EUV falters, chip makers will scale cell libraries to shrink chips. Imec is working on a three-track library that represents a 0.52x shrink of the seven-track libraries that chip makers use in their leading-edge 10-nm processes today.
The trade-off of this work is that it enables a 3-nm node but only leaves room for one FinFET per cell, down from three today. In addition, engineers can expect to face new design restrictions as cell tracks shrink, something already starting at 7-nm nodes.
Imec is working on several designs that could ease the pain. They include so-called super-vias that link three rather than two levels of metal and power rails buried deeper in the design to save space.
The work suggests that designers may be forced to move to nanowire transistors at 3 nm for processes based solely on immersion steppers. With EUV, however, a 3-nm process might still have room for five-track cells and thus be based on FinFETs, said Steegen.
Processes using only immersion steppers can shrink tracks in cell gate libraries, but they sacrifice the number of FinFETs (green) as gates (red) shrink. At the bottom, Imec shows four structures that it is developing to mitigate efforts of the shrinks. Click to enlarge.
In any case, there’s little doubt that system, chip, and process engineers will need to collaborate more closely than ever at these fine nodes. They will need to determine what functions can be integrated on a single die or whether they need to be made in separate die and, if so, how those chips will be linked.
Meanwhile, a basketful of new memory architectures are still in the lab. MRAM currently is the most promising one as a replacement for SRAM cache and even DRAM, said Steegen. However, MRAM likely will need new transistor structures below 5 nm.
The laundry list of other interesting options includes a spin-orbit torque MRAM and ferroelectric RAMs as DRAM replacements. The industry is working on at least five candidates for storage-class memories, mostly variants of crossbar and resistive RAM structures, Steegen said.
Imec is doing work on a version of OxRAM that could be useful for designs targeting the Internet of Things. It has already tested one approach capable of withstanding the temperature requirements for automotive designs.
Despite the mind-numbing options and challenges, Steegen remains optimistic. Before starting a talk to some 1,800 attendees here, she took a flash poll that showed that 68% of the audience believed that the industry will get to nodes beyond 3 nm.
“Thanks for all of you who said ‘yes’ to this possibility, and for those who said ‘no,’ I’ll prove you wrong,” she quipped.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times