LAKE WALES, Fla.—Researchers from IBM this week are describing a breakthrough in 60-gigabit-per-second (Gb/s) optical interconnect that the company claims will lead to broad replacement of costlier 56 Gb/s copper interconnects.
At the 2017 Symposia on VLSI Technology and Circuits, in Kyoto, Japan, scientists from IBM Research in Zurich will describe an inexpensive 60 Gb/s optical receiver that is expected to be followed next year by a matching optical transmitter. Together, the two devices will form a complete optical-transceiver built in CMOS at costs that the company expects to be lower than the costs of a copper interconnect.
IBM reports a low power implementation of a 60Gb/s optical receiver (RX) cast in 14-nanometer CMOS finFETs with high jitter tolerance using digital clock and data recovery. (Source: IBM)
"We are developing a single lane 60-Gigabit per second optical receiver with non-return to zero (NRZ) signaling targeting low cost multi-mode vertical-cavity surface-emitting laser (VCSEL) based links," Alessandro Cevrero, an engineer at IBM, told EE Times in advance of the symposium.
"The power is way lower than our competitors, ~120mW for the receiver and eventually below 300mW for the full transceiver," Cevrero said. "Also, its compact CMOS footprint and low power consumption means it can be moved closer to the processor or switch chip and eventually even be put in the same package or even on processor chip die, providing high bandwidth connectivity directly from the processor or switch chip spanning up to 100-meters. This covers links from processor-to-processor, processor-to-memory, from drawer-to-drawer inside a rack and from a rack to a tier-1 Internet switch."
Alessandro Cevrero, an electrical engineer at IBM Research in Zurich, demonstrates IBM's low-cost silicon photonics receiver.
Cevrero said that implementing the devices in CMOS enabled IBM to essential double transmission speed, essentially cutting the costs per Gigabit per second by two. "Some people believed that a SiGe solution was required to achieve good optical sensitivity at data rates above 32Gb/s," Cevero said. "Our work demonstrates that CMOS can achieve the same sensitivity, but at much lower power consumption.”
The 60 Gb/s optical link IBM demonstrated still depends on discrete III-V photodetectors (for the receiver) and discrete III-V lasers (for the transmitter) together forming a transceiver that is otherwise all-CMOS. Others, such as Intel (which offers a 25-Gigabit per second optical transceiver), use silicon photonics to modulate the light from a III-V lasers. Intel combines four such channels to achieve 100-Gbits per second today, but at much higher cost and power consumption, according to IBM. Intel, however, is shooting for the same goal as IBM by 2020.
IBM's current prototype runs at a wavelength of 850 nanometers, which is the standard wavelength for VCSEL-based multi-mode optical links, making it suitable for processor-to-memory, processor-to-processor and server-to-server communications. Once the complete transceiver is demonstrated later this year or early 2018, the price crossover point will have been reached, according to Thomas Toifl, manager of the high-speed Interconnects group at IBM Research in Zurich.
The entire 60-Gigabit per second optical receiver fits on a small CMOS die, or could be incorporated into the edge of a processor, and consumes only 117 milliwatts. (Source: IBM)
"So far, optical links were always pushed out due to their higher costs, but now we have reached the point where optics are at the same price as electrical links," Toifl told EE Times in advance of the VLSI Symposium. "Electrical links, however, need complex equalization when we go to higher data rates, and hence require more power. Also, their distance is limited to about two meters of cable compared to 100 meters for our optical solution."
Toifl also claimed IBM's "breakthrough" CMOS photonics technology provides superior sensitivity ( -9dBm) and is ideal for the high throughput requirements of cloud computing. The team also claims to have pushed its existing CMOS circuitry to 70+ Gigabits per second already, but is waiting for the III-V photodiodes and vertical-cavity surface-emitting lasers to catch up before publicizing it.