MADISON, Wis. -- Imagination Technologies revealed a key to its effort to make MIPS processing cores indispensable in automotive and industrial applications that require functional safety by rolling out Wednesday (June 13) a high-performance, multi-threaded MIPS CPU IP called MIPS I6500-F.
The new core “comes with significantly higher computing power and performance,” Tim Mace, senior manager of business development for Imagination's MIPS business unit, told EE Times. It stands apart from competing CPU processing cores — from ARM, for example — whose functional-safety cores are widely available but in deployments limited mostly to embedded systems, he explained.
Despite Imagination’s recent decision to put the company’s MIPS business on the block as it fights for survival in the midst of a "dispute resolution procedure" with Apple, Imagination has not stalled its MIPS engineering goals. The mission of the I6500-F is to breathe new life into Imagination’s MIPS portfolio.
The team designed the I6500-F with a single purpose: Enabling a new generation of SoCs critical to more powerful, compute-intensive systems demanding functional safety.
MIPS revealed that the I6500-F is already at the heart of Mobileye (soon to become a part of Intel)’s upcoming EyeQ5 SoC, scheduled for sampling in 2018. With processing power of 12 Tera operations per second and power consumption below 5W, EyeQ5 will be one of the key SoCs powering the highly anticipated BMW/Intel/Mobileye’s autonomous car platform.
Supporting heterogeneous architecture
The MIPS I6500-F builds on the popular MIPS I6500 CPU — a 64-bit, multi-threaded, multi-core, multi-cluster CPU that’s scalable from embedded to cloud.
With its ability to scale up to 64 heterogeneous clusters of multi-thread multi-core MIPS CPUs, MIPSI6500-F will be ideal for CPUs that operate in “a heterogeneous computing architecture,” explained Mace.
Next page: ASIL B(D)?