CUPERTINO, Calif. – A U.S. research effort aims to nurture an ecosystem for designing semiconductors from plug-and-play chiplets. It arrives at a time when rivals such as Intel and Xilinx are using proprietary packaging techniques to differentiate competing FPGAs.
Over the next eight months, the Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program under the Defense Advanced Research Projects Agency aims to define and test open chip interfaces. Within three years it hopes multiple companies will use the links to connect a wide range of die to form sophisticated components.
Intel has signed up for the program, and others are expected to follow soon. Internally, the x86 giant is debating whether to open up parts of its embedded multi-die interconnect bridge (EMIB) as part of its participation. The company gave the most detailed look at EMIB to date at the Hot Chips event here.
Several executives from Xilinx, which pioneered the cache coherent serial interconnect (CCIX) have expressed interest in the DARPA program. The company announced its fourth-generation FPGAs using the proprietary CoWoS 2.5-D packaging technology from TSMC.
Just what approach could bring low cost, high bandwidth connections to mainstream semiconductor design is unclear.
Intel positioned EMIB (center) between board and die links. (Image: Intel)
Multichip modules using organic substrates have been available for many years. Some vendors are said to be driving the relatively low cost approach beyond its also relatively low density levels.
TSMC pioneered a form of wafer-level fan out used to package applications processors and their memory in Apple’s latest iPhones. The technique offers greater density than MCMs but not enough to handle wired processors.
High-end AMD and Nvidia GPUs have joined Xilinx FPGAs in using 2.5-D techniques such as CoWoS to link processors and memory stacks. However, to date they are too expensive for consumer products, said a senior Microsoft engineer who rejected the approach for the Xbox.
Like Microsoft, AMD took a pass on the relatively expensive 2.5D stacks for its Epyc server processor built from four die on an organic substrate. The more traditional MCM “is well known technology and lower cost…there were some [performance] trade-offs, but we think they were appropriate,” said Kevin Lepak, who described the chip here.
Several sides expressed hopes the DARPA program can cut through the complex technical and business barriers. “We want chiplets to become more like IPs,” said a senior architect from Xilinx.
In 2014, Intel first described its EMIB as an approach with the capabilities of 2.5-D stacks at lower costs. That’s in part because it uses just a sliver of a silicon interposer to bridge between any two sides of any size die.
Altera tried the approach before it was acquired by Intel. The Intel division now ships high-end Stratix FPGAs using EMIB to link to DRAM stacks and transceivers.
Next page: EMIB’s interfaces and a CCIX update