TAIPEI — Xilinx, ARM, Cadence, and TSMC have announced a partnership to build a test chip in 7-nm FinFET process technology for delivery next year that promises to speed data center applications.
The chip will be the first demonstration in silicon of Cache Coherent Interconnect for Accelerators (CCIX) enabling multi-core high-performance ARM CPUs working via a coherent fabric with off-chip FPGA accelerators, said the partners in a press statement.
Accelerating applications in data centers is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, and network processing benefit from acceleration engines that move data effectively among various system components.
CCIX will allow components to access and process data irrespective of where it resides without the need for complex programming environments. CCIX will use existing server interconnect infrastructure and deliver higher bandwidth, lower latency, and cache coherent access to shared memory.
This will result in a significant improvement in the effectiveness of accelerators as well as overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership of acceleration systems.
The test chip, implemented on TSMC’s 7-nm process, will be based on the latest ARM DynamIQ technology, CMN-600 coherent on-chip bus, and foundation IP.
“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager of ARM's Infrastructure Group. “The test chip will not only demonstrate how the latest ARM technology with coherent multichip accelerators can scale across the data center but reinforces our commitment to solving the challenge of accessing data quickly and easily.”
To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe-4/3) IP solution (controller and PHY), DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip.
The test chip provides connectivity to Xilinx’s 16-nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.
“Our Virtex UltraScale+ HBM family is built using TSMC’s third-generation CoWoS technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX," said Victor Peng, chief operating officer at Xilinx.
The test chip will tape out early in the first quarter of 2018, with silicon availability expected in the second half of 2018.
“By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7 nm and other advanced nodes for these growing data center applications,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”
Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics, and healthcare, according to Cliff Hou, TSMC vice president, Research & Development/Design and Technology Platform.
“TSMC’s most advanced 7-nm FinFET process technology provides high-performance and low-power benefits that satisfy distinct product requirements for High-Performance Computing applications targeting these markets,” said Hou.
— Alan Patterson covers the semiconductor industry for EE Times. He is based in Taiwan.