Processor IP vendors Andes and Cortus announced plans for RISC-V compliant cores earlier this year. The relatively small players are expected to eventually transition to the open-source architecture.
“It’s hard to put your finger on big market success for RISC-V yet because it’s too early to see SoC and systems shipments,” said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, California).
“SiFive is certainly making good progress, and with the U54, it can now go after a broader range of embedded designs. The previous products were limited to use with an RTOS or other microcontroller-like designs.”
As for vendor support, “there’s been a surprising amount of work on RISC-V Linux systems to date using simulators and emulators,” said Kang. “Getting silicon will help spur the software ecosystem.”
UltraSoC recently joined Rambus as a member of SiFive’s third-party IP program called DesignShare, providing trace and debug tools and SoC monitors. SiFive aims to announce several more IP partners before the end of the year.
Separately, engineers hope to define a vector version of the RISC-V instruction set by the end of the year, targeting applications such as machine learning. A hypervisor mode is also in the works to enable virtual machines on RISC-V.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times