SAN JOSE, Calif. — Intel and Globalfoundries will describe their 10nm and 7nm process nodes, respectively at the International Electron Devices Meeting (IEDM) in December. The event also will host papers pointing to new directions in memories, medical and flexible electronics and transistors beyond today’s FinFETs.
Intel will discuss several aspects of its 10nm node first unveiled in March. It sports FinFETs with a 7nm fin width at a 34nm pitch and a 46nm fin height made using self-aligned quadruple patterning. A 204 Mbit SRAM made in the process packs separate high-density, low voltage and high-performance cells that measure from 0.0312µm2 to 0.0441µm2.
The 12-metal interconnect layers in the node can support multiple threshold voltages. Compared to its 14nm process, the 10nm node sports NMOS and PMOS current that is 71 percent and 35 percent greater. Cobalt wires in the lowest two metal layers offer up to 10x improvement in electro-migration and a 2x reduction in via resistance.
For its part, Globalfoundries will detail a 0.0269µm2 SRAM cell made in its 7nm FinFET process tat was discussed at a September company event. Compared to its current 14nm process licensed from Samsung, the 7nm node should deliver 2.8x better routed logic density and more than 40 percent more performance or 55 percent lower power.
Like Intel, the Globalfoundries node will support a range of threshold voltages. It uses self-aligned quad patterning to make fins and double patterning for metallization.
A handful of papers will provide a view of research on the possible successors to the FinFET as a basic electronics switch.
Imec researchers will present at least three papers on the subject, including oneon what it claims is the first circuit built with stacked silicon nanowires. The working ring oscillator used a new metallization process for n-type devices that led to greater control of threshold voltage.
The MOSFET structures essentially wrap a gate around a nanowire to act as a transistor channel. In a separate paper, Imec will report performance characteristics of nanowires and nanosheets, arrays of the gate-all-around nanowires. Vertical test devices built in InGaAs showed Ion performance of 397µA/µm and peak transconductance of 1.6S/µm at Vds=0.5V.
Separately, Globalfoundries will describe a ring oscillator built with 14nm ferroelectric FinFETs. It ran at the same frequencies but lower power than similar devices in silicon. The doped hafnia structures have negative capacitance, so they could be used in commercial fabs, it said.
In memory papers, Macronix will report an advance in 3D NAND and SK Hynix will share work on ReRAM. In addition, IBM and CEA-Leti will give separate talks on their work in monolithic 3D integration.
In heath care, Swiss researchers will describe a low power sensor made using FD-SOI that can collect and measure in real time biomarkers from sweat. Separately, a team led by the Houston Methodist Research Institute will describe implantable devices enabling controlled release over time of drugs or hormones via nanofluidic channels.
Pointing to new directions in flexible electronics, researchers from the University of Texas at Austin will discuss how they built a variety of two- and three-terminal graphene and MoS2 devices on paper. The graphene devices achieved a record 25 GHz cutoff frequency and performance remained high even when the paper was rolled into a two-inch diameter roll.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times