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Monolithic 3D Shows Promise, Challenges

Major gap in lack of EDA place-and-route
10/23/2017 00:01 AM EDT
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mendicant98
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yes, scaling is not over...
mendicant98   10/24/2017 10:15:10 AM
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...but M3D must not be set aside or discounted, either. Leti showed, two years ago at Semicon West, that a 2-layer M3D construct at 14nm had equal or better performance than a 1-layer 10nm technology. And 3-layer stacking increased the performance. Meaning, a 28nm node can sustain itself even longer, if deployed with M3D in 2-, 3-, or (better) more layers. Using the high yields of an older node, whose manufacturing equipment has already been fully depreciated, can only mean low costs. (Of course, that's not so good for the Lam Research or Applied Materials business models; but, is a discussion for another time and place.) Some of the thermal uncertainties have been addressed in the archival, scientific literature. However, heat dissipation becomes a complex problem, especially for M3D logic structures. Coupling 3D EDA to rapid-throughput thermal modeling and assessment is essential, and another so-far-missing element of the EDA and design space. Cost and processing complexity for M3D have been, and are being, addressed. MonolithIC3D and others have made advancements, starting from the 3DNAND processing architectures, and innovating from there. Thanks for a nice summation of an event I wish I had been able to attend...

Or_Bach
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foundries vs. scaling..
Or_Bach   10/24/2017 7:52:08 AM
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Clealy dimension scaling is not over.

Yet, GF is pushing strongly FDSOI as scaling alternative, clearly stating that for many customers dimension scaling is the wrong path. And TSMC just stated "About 23 percent of TSMC's third-quarter revenue came from 28nm products, and the company had its highest number of tapeouts at that node during the period", according to Wei. So yes, the industry should adapt monolithic 3D now, as for many application it is the best path  

photonic
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Re: ....
photonic   10/24/2017 2:25:24 AM
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The foundries don't agree that scaling is over and are putting their money into 7 and 5 nm geometries.

bec0
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Re: ....
bec0   10/23/2017 11:08:22 PM
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I totally agree. The foundries should get on board with this post-scaling movement. The benefits are huge. They should evaluate all the offerings and ideas, and choose to work on the simplest and easiest to manufacture solution, i.e. lowest cost. The foundries can lead the way, and make a pile of $$$$. Who's first???

Or_Bach
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Monolithic 3D value
Or_Bach   10/23/2017 8:40:28 PM
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The value monolithic 3D provides is very high even if both layers have FEOL and BEO. There multiple application in which monolithic 3D provides multiple order of magnetude advantage: *Using it to overcome the memory wall as been detailed in the DARPA 3DSoC program and in our S3S paper would benefit computer system by about 1,000x

*Using it for image sensor would increase  the dynamic range by 30 DB

*Using it for redundency, allowing Wafer-Scali-Integration, could enhance system value by more than 100x, 

*Using it forperiphery over cell would improve memory product by more than 100x

*...    

realjjj
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CEO
....
realjjj   10/23/2017 1:09:42 PM
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The way I frame this, if both layers have FEOL and BEOL, there isn't much upside. If the top layer has FEOL and only some BEOL, it starts to get more interesting. Then maybe second layer fab after bonding and beyond that muti-tier FEOL. The holy grail being a way to manufacture this multi-tier FEOL cheaply with process steps that address multiple tiers at once (some would say like 3D NAND). You can compare the early stages with TSV, some upsides but at a cost. However, the real goal is much cheaper transistors, enabling solid cost scaling and much higher efficiency that fits the systems of the future.

The foundries should be on the forefront of this. Not only that the first one to get there disrupts the market but they could transition from a few MB of SRAM on a SoC to many GB of NV memory and that's a huge expansion of the foundry TAM.

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