SAN JOSE, Calif. — Samsung will describe a 7nm SRAM made with extreme ultraviolet lithography (EUV) at the International Solid-State Circuits Conference in February. Other ISSCC papers will detail memories, sensors and processors spanning everything from fast DRAMs to location trackers embedded in a boot.
Reinforcing its commitment earlier this year to be the first chip maker to use EUV, Samsung will describe a 0.026μm2 SRAM bit cell in a 7nm process it aims to make available next year. The chip is the smallest SRAM described to date and uses a double-write driver to reduce minimum supply voltage.
Two papers on specialty memories should attract attention. TSMC will describe an 11 Mbit resistive RAM macro made in a 40nm process. It uses a new sense amplifier TSMC claims offers a 58 percent faster access speed as well as a new write scheme to improve endurance and retention.
Separately, Japan’s Semiconductor Energy Laboratory will discuss a 60nm crystalline oxide semiconductor FET used in a deep-learning accelerator due to its speed and low power. The Kbit cell can be read in 45ns and written in 20ns, drawing 97.9pJ and 123pJ of energy.
Papers in more conventional DRAM and flash sessions show stepwise advances with few surprises.
Samsung and SK Hynix will describe 16 and 8 Gbit GDDR6 DRAMs, respectively, with maximum data rates of 16-18Gbits/s/pin using single-ended signaling. SK Hynix also will detail its eight-layer HBM2 that delivers 64 Gbits of memory on a 341 GByte/s interconnect.
In flash, Samsung will present its much-discussed Tbit NAND based on 64 stacked layers and four bits/cell. Toshiba and Western Digital will counter with a 512 Gbit design using three bits/cell in a 96-layer stack. Separately, Samsung will describe its Z-NAND that achieves a 15μs latency as well as a solid-state drive controller for it that aims to compete with Intel’s Optane drives.
Next page: Sensor finds its way in a boot