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UMC Files Countersuit Against Micron

1/15/2018 00:01 AM EST
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BrianO2
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BrianO2   1/31/2018 11:11:55 AM
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I totally agree with you!

ubm112211
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ubm112211   1/17/2018 10:27:31 PM
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yep, memory vendors have been playing underdogs most time in history. now when they team up they can beat cpu vendors to its knees. stange logic , any customer want higher asps? 

realjjj
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realjjj   1/17/2018 6:02:28 AM
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In practice,  they need higher ASPs in PC as units decline and they have to do it while there is competitive pressure. A focus on HBM+EMIB+a GPU die might be likely and high DRAM prices could be seen as a positive as it boosts their ASPs. In server maybe they can try to leverage XPoint to reduce the amount of DRAM used but remains to be seen if that works out - ofc the driver would be to generate more revenue, not some war on DRAM. Hmm, interesting thing here, Intel offers somewhat limited memory bandwidth and PCIe connectivity with their server SKUs as a way to boost CPU units sales. AMD is exploiting this now with Epyc and Intel will have to adjust their strategy. Maybe they'll try to leverage their proprietary interface to XPoint while keeping the current DRAM BW and PCIe connectivity limitations, not sure, need to digest this.

Edit - stumbled upon this blog post and thought it's worth sharing https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/arm-at-smc

realjjj
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realjjj   1/17/2018 5:22:07 AM
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As far as I can recall, UMC is aiming to ramp 32nm DRAM when others are ramping 1y. That's almost a decade behind.

resistion
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resistion   1/17/2018 1:49:17 AM
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PCM performance is very far from DRAM.

Shinobee
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Shinobee   1/17/2018 1:42:33 AM
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I think xpoint has potential to be useful.  Though I was always under the impression that a DRAM role memory may require an endurance of around 10^12 W/E cycles.  I haven't seen strong evidence that PCRAM is capable of that at latest node sizes.

resistion
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resistion   1/17/2018 1:17:30 AM
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They need something to fulfill the DRAM role for their system, only leverage is the XPoint.

Shinobee
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Shinobee   1/17/2018 12:09:22 AM
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Just to add to this point and I could be wrong but I was always under that Intel viewed DRAM as a bottleneck and designed an architecture that minimized its dependency.  Particularly when CPUs started breaking the 1ghz barrier (greatly exceeding DRAM latencies) they resorted to expand L2 and L3 caches in the front end micro-op layer while maintaining a "load store" execution core.

ubm112211
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ubm112211   1/16/2018 10:57:35 PM
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答:联电要自主研发DRAM技术。联电在晶圆代工市场多年,长期投入研发已有很好的技术实力,连最先进囗最复杂的14奈米逻辑IC制程都自主研发成功并开始投產,而且许多DRAM技术与联电既有的逻辑技术相通。至于在DRAM特有技术部分,则透过公开的技术报告、逆向工程方式了解,再依据开发路线落实。事实上,DRAM工作原理没有改变,现今的DRAM只是藉由更先进的制程技术,达到每位元更低成本的目标,操作原理与15年前研发DRAM时相同。 http://www.sohu.com/a/212799210_507112

resistion
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resistion   1/16/2018 10:08:51 PM
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Maybe it was easier then, but they didn't run with it very far either.

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