SANTA CLARA, Calif. — Vendors and researchers are making significant progress applying machine learning to the thorny issues of chip design, according to a panel at DesignCon here. The use of AI in EDA was a hot topic that drew a standing-room-only crowd to the panel and spawned several papers at the event.
Over the past year, the Center for Advanced Electronics through Machine Learning (CAEML) has gained four new partners. The team of 13 industry members and three universities has expanded both the breadth and depth of its work. CAEML is funded in part by a National Science Foundation program.
“Last year, we focused mainly on signal integrity and power integrity, but this year, we diversified our portfolio into system analysis, chip layout, and trusted platform design — so the diversity of the research has made the most progress,” said Christopher Cheng, a distinguished technologist at Hewlett-Packard Enterprise and a member of CAEML.
“Work in Bayesian optimizations and convolutional neural networks in design-for-manufacturing have both advanced significantly in the capabilities we have demoed, and we’re starting to think about use of in-line learning in the design process,” said Paul Franzon, a distinguished professor at North Carolina State University, one of the group’s three host colleges.
“One of the challenges we face is getting access to data from companies,” said Madhavan Swaminathan, a professor at Georgia Institute of Technology, another CAEML host. “Most of their data is proprietary, so we’ve come up with several mechanisms to handle it. The processes are working fairly well, but they are more lengthy than we’d like.”
The group had a sort of coming-out party for itself at this event last year. It started with backing from nine vendors including Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung, and Xilinx. Its initial interest areas included high-speed interconnects, power delivery, system-level electrostatic discharge, IP core reuse, and design rule checking.
Cadence sketched out a roadmap suggesting that the EDA industry is entering a second phase in its use of AI. Click to enlarge. Source: Cadence.
EDA vendors such as Cadence Design Systems started following research in machine learning back in the early 1990s. The techniques first made their way into its products in 2013 with a version of Virtuoso that used analytics and data mining to create machine-learning models for parasitic extraction, said David White, a senior director of R&D at Cadence.
To date, Cadence has shipped more than 1.1 million machine-learning models for its tools to speed lengthy calculations. The next phase of product development is in place-and-routing tools that learn from human designers to recommend optimizations that speed turnaround time. The solutions may use a combination of local and cloud-based processing to harness parallel systems and large data sets, said White.
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