SAN FRANCISCO — Intel claimed that it maintained Moore’s law scaling with a 10-nm SRAM that it described here at the International Solid-State Circuits Conference (ISSCC). However, Samsung followed by describing a smaller 256-Mbit SRAM made with extreme ultraviolet lithography and expressed confidence in EUV.
Intel described 0.0312-mm2 high density and 0.0367-mm2 low-voltage SRAM bitcells made in its 10-nm process. Samsung’s 6T 256-Mbit device has a 0.026-mm2 bitcell.
The Intel design shows 0.62–0.58x scaling compared to its 14-nm SRAM, maintaining Moore’s law and “within 15 percent of the smallest reported 7-nm cell,” said Intel’s Zheng Gui, pointing to smaller 7-nm SRAMs from Samsung this year and TSMC at ISSCC 2017.
But can Samsung make its SRAM with EUV in volume? “Having real, working silicon lowered our concerns,” said Taejoong Song, a vice president in design enablement, who presented the paper for Samsung.
The paper described techniques to reduce by 75 percent bitline resistance, one of the biggest challenges for the design. It also described techniques to reduce by about 20 percent problems with variation in minimum voltage levels. Song also noted that EUV enables more design flexibility in the number of vias used.
Intel designed read/write-assist circuits that lowered aspects of its 10-nm SRAM’s power as much as 40%. Source: Intel.
Using the popular metric of power, performance and area (PPA), “EUV takes care of area, and design techniques take care of PP,” said Song after his presentation.
The fully validated design used EUV on at least four to six layers. However, Song declined to provide any update on Samsung’s plans for commercial use of EUV.
“My big takeaway is that Intel is behind. When have you seen Intel get on the stage and say they are only 15 percent behind?” asked one analyst who attended the sessions.
Others were more skeptical. “TSMC and Intel are much more conservative on EUV, and there are probably reasons for that,” said David Kanter of Real World Tech. “Consider the yield implications given how few EUV wafers people have run so far.”
As a memory vendor, Samsung may be more concerned about SRAM size than the x86 giant, said Eli Harari, a NAND flash pioneer who attended the sessions. However, he expressed confidence that the potential returns on future chip generations are so big that the top chipmakers will “suffer quietly” with the cost and technical issues of EUV.
For its part, TSMC presented an L1 cache compiler now available for its 7-nm process that can operate at data rates up to at least 4.4 GHz. Its 16-nm L1 memories topped out at about 3 GHz. The higher data rate is particularly useful for matching the speed of high-speed CPUs and mobile applications processors.
Samsung has fully validated its 256-Mbit SRAM made with EUV. Source: Samsung.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times