TSMC will start risk production on its first-generation 7nm process next month. It expects in May the first of 12 tapeouts in the process this year, and a total of about 20 tapeouts in the first 12 months.
The process should deliver 3.3x greater routed gate density and either 35 percent more speed or 60 percent less power than the foundry’s 16FF+ node. The process includes new cell libraries, cache macros and serdes.
The foundry is developing unique flavors of its processes tailored to the separate needs of automotive, smartphone, high-performance computing (HPC) and IoT markets.
The 7nm HPC platform includes a new design flow being released in June as well as enhanced IP and process optimizations. It drove an ARM A72 to more than 4 GHz. The platform also supports on-chip magnetic inductors to create integrated voltage regulators.
The HPC platform includes high performance transistors that deliver a five percent speed gain over the vanilla 7nm process. Interestingly, TSMC described several techniques driving advances of 4-5 percent across various processes, suggesting the foundry is squeezing out gains wherever it can find them. An automotive variant of the 7nm process will be ready next year.
Just how little volume TSMC is getting at its advanced process nodes is not clear.
One TSMC executive said the foundry expects a steep ramp for its 10nm node to 400,000 total wafers this year. He forecast TSMC will make three times as many 10 and 7nm wafers total in 2019. Another executive said volumes of 10nm wafers will surpass 16nm wafers this year.
The 10nm node is expected to be a short lived one, created in large part for Apple’s iPhone 8. It sports twice the gate density, and either 10 percent higher speed or 25 percent less power than the 16nm node, TSMC said.
TSMC had little to say about either its 10nm or 5nm nodes except ramping 10nm was a primary focus of this year and 5nm will be in volume production in 2020. Previously TSMC suggested it would start use of EUV at 5nm.
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