Figure 1 depicts an
efficient automated flow for applying voltage-dependent design rule
checking (VD-DRC) with a DRC sign-off deck from the foundry. The flow
starts with identifying and defining the supply voltages for the design,
then using the voltage propagation functionality to propagate supply
voltages to internal design nodes (based on user-defined rules for the
propagation criteria for every device type). The user can then
incorporate the DRC rules in the Calibre PERC logic-driven layout (LDL)
functionality , to perform the DRC checks directly, or generate
text markers to be used later with the DRC sign-off deck. Errors can be
debugged with a results viewing environment (Calibre RVE™ in our example).
This debugging environment can help the user debug results from the
topological perspective for voltages propagated to internal nets, as
well as from the geometrical perspective. Figure 2 illustrates the
high-level data flow for this automated approach.
Figure 1: An automated flow for applying VD-DRC checking to a design.
Figure 2: High-level data flow for automated VD-DRC.
Let’s look at a specific rule example:
Metal2 polygon spacing between two nets should be >= 0.5 um
if the voltage difference between these two nets is greater than 40V
Figure 3 illustrates the end result, a portion of the design where violations of this rule are highlighted (red arrows).
Figure 3: Rule check violations.
Spotting these violations requires several steps:
- Define the supply voltages for this design.
the supply voltages through devices to the internal nodes, which
results in attributes for the minimum and maximum voltage that every net
can see. These attributes are reported as ranges for the internal nets.
- Annotate these ranges to the polygons of these internal nets.
4 demonstrates how the results are reported from the topological
perspective in the debug environment. As shown in the results, nets
“OUT2” and “OUTA” are from different voltage domains, where the
difference between the maximum voltages propagated to these nodes is
(50V – 5V = 45V). This difference is greater than the 40V that the rule
checks for. Therefore, the spacing for metal2 polygons between these two
nets must be verified against the 0.5 um constraint.
Figure 4: Portion of the topological results identifying conditions requiring additional checking.
addition to debugging the voltages from the topological perspective,
the user can also debug the results from the geometrical perspective
using the results viewer. Figure 5 illustrates that there are two
violations for our rule, where the spacing was 0.25 um and 0.3 um. These
violations are the ones highlighted in Figure 5.
Figure 5: Portion of the geometrical results showing the two violations.