Intel’s Krzanich: CEO Q&A at IDF

In 2014 their op income (looked up the numbers to be accurate) PC 14.635 billions , Server 7.279B , Mobile (4.206)B , IoT 0.616B , Software 0.055B , All Other (3.009)B.

So you can say that PC was 100% of income since all else adds up to close to 0.  Mobile was the first knock-down for PCs, foldable screens in phones will be the second knock-down even if nobody seems to factor that in yet. Later on glasses would likely KO the PC.  Factor in all else, mobile and contra revenue, IoT, Altera, xpoint, foundry, AMD's Zen , ARM in server and it doesn't add up. So far Intel has managed to keep PC income up by offering less and charging more but that won't work forever. Tough times ahead.

"We said it's a high speed switch, a stacked 3-D array. People keep asking if its phase change. We've said it uses bulk properties. It's a bit different from phase change. That chemistry is very unique. It's not a pure phase change because it uses bulk material properties." They seem to think phase change is not a bulk material change. But any bulk change of resistance implies a change of bulk resistivity. That is hard to do without a microstructural change. If it is not phase change, it has to be something very analog.

EET:  Those 15 EUV steppers purchased from ASML, was that your purchase order?

Krzanich:  [Silence] Some body bought a lot of them.

"It will take another year or so of effort to know if we will have EUV for 7nm or not."

So they didn't come right out and admit to buying them. That is very interesting. It was said to be a key US customer right?

Rick!
Since you asked about Fab 42, did you ask him about what is going on in Israel?  Apparently they began work on upgrading old Fab 18 for 300mm and 10nm and upgrading Fab 28. There is silence about this huge project in the amount of US$6B. What is going on there?

I am echoing this comment below that Sunit Rikhi posted pubically on the LinkedIn thread for this story:

"...To complement Brian's answer, I just want to add that one of the reasons why I felt comfortable with my decision to retire is my strong sense that Intel Custom Foundry is at the point of being a self-sustaining irreversible force."

@resistion: Yeds ASML said it was a US buyer meaning it could be GloFo or IBM or I suppose Samsung Austin.

G. Dan Hutcheson has written that running pilot production with about 15 EUV machines should give the user statistical data with about an 85-90% confidence level how they will perform in actual production.

But those sites did not have a pre-existing EUV system, I think they used the one at CNSE or IMEC?

Is Samsung a key "USA" customer?? I think not. My bet is on GloFo, that has two times the foundry revenue of Samsung and it is a little more "USA" than korean giant. After all Austin Fab is only a production Fab, all the research is done in korea.

I have the suspect "some body" wants to speedup the 7nm shipment bypassing the long R&D stage to study if the early adoption is good or bad for yields and gross margin. Or maybe "some body" have right now realized that present EUV is better than nothing  not being able to spend billions to have the right four/five patterning process ready to go on 7nm. Or maybe "some body" has not the Intel Ownership at ASML, so is purchasing now to not be the last one in a couple of years; almost sure Intel has an absolute precedence on scanner orders of other companies. The last hypothesis points at GloFo again.

Regardless who bought the EUV machines, I doubt Intel has this "absolute precedence" over all other company, or if it does it is only because of their investment in ASML. No way ASML sales volume to Intel is so much higher than that of Samsung or TSMC on pure quantity of scanner orders per year. Intel has always been very shrewd with capex, especially on litho spending with TSMC and Samsung buying into the new technology more quickly and at higher volumes. Really, Intel shown it can use the older cheaper scanner technology longer than the rest and still stay ahead in the advanced nodes.

My opinion is it is Intel that is biyong the 15 EUV steppers, as G. Dan Hutchison speculates, to start getting statistical data on their performance so they can (hopefully) insert them into a 7nm flow.

The thing is, Intel would not be getting all 15 in the coming year. On the other hand, in a year or so they need to know EUV 7 nm viability.

 So a little more 3DXPoint ™ insight
Krzanich
".... It's a bit different from phase change. That chemistry is very unique. It's not a pure phase change because it uses bulk material properties...."

So its only a bit different from phase change. Its not a pure phase change.
Is there such a thing as an impure phase change? One interpretation of what was meant was it involves an incomplete phase change. Possibly meaning the bulk material is in the form of a crystal-amorphous mix. The phases on a phase diagram usually include those with: liquid, amorphous, crystal-liquid or crystal amorphous mix and crystal. Moving between those phases is a phase change Mr Krzanich.

With such a mix it is just possible, for example, to use differences in switching delay time of the bulk material to store data. Where an automatic read/refresh maintains the shortest delay time logic state. It is thermally sensitive, however, it does provides a very fast write/erase potential. You will find the outline in US patent 4,199,692 " Amorphous Non-Volatile RAM" filed by a believer during a time of innocence. There may be other subtle structure related detectable parametric changes in the same phase of a bulk material that could be employed and would not be a phase change.

It was also pointed out to me that Intel 10 nm is equivalent to foundry 7 nm based on metal pitch. In that case they would need multiple patterning even with the current EUV tools.

Seems like continued delay of Fab42 until something "worthy" of the enormous capex required to fill and operate it, strategy which started with putting 14nm in the other arizona fabs at the 11th hour instead of commissioning/startup of F42. To me, the decision to proceed D1X Mod2 new construction AFTER mothballing F42 is more interesting. They built 200k sqft in Arizona, mothballed it, and built basically the same 200k sqft again in Oregon to use instead. Basically that Intel was suddenly far more committed to "large scale development" if that's what the largest single fab in Intel's entire arsenal is used for, than pure manufacturing capacity : ie, volume production requirements decreasing, and development becoming more intense. This whole recent tick tock skip at 14nm and 10nm delay looks inevitable in retrospect.

@m00nshine: Does this suggest those 15 EUV systems may go to an expanded Oregon development fab?

Strange, what happened to Fab 42. Cancelling that was bigger /more impact than this EUV order.

Personally I can't imagine committing them all to one fab right away, but the D1X Mod1/Mod2 fab is the only US fab complex large enough to house them all at once In the future, the space needs won't be as large if you can put all the vhips on the table and commit to no or very limited double patterning. But in the mean time, you're talking inserting EUV into current production fabs full of all the litho/etch/films tools needed for double patterning and that's just a gamble because it's taking away a huge amount of valuable production area.. D1X is probably big enough to put in a bunch of EUV machines alongside those tools for double patterning for a full side by side evaluation plus it would have been a clean slate to work with. That seems awfully wasteful, though, even for Intel

Rick and m00nshine, D1X mod 2 is most reasonable choice agreed BUT the power requirements have not been determined yet. I mean wall plug power. That affects the footprint. Presumably larger power larger footprint. Power is added serially: http://optics.org/news/6/6/31

Yes they have a ownership thanks to their investiments. Moreover i think that regarding EUV scanners, they will be the largest customer around by a wide margin. Remember that finer nodes will become only a portion of TSMC shipment, the bulk of the production will stay on "older" nodes for a while. About Samsung it is not a major EUV customer, their  logic division is small (half of GloFo shipment), and memory division (the largest one) do not  need of EUV scanners in upcoming years, it will be all stacking with conservative nodes "under" 40nm.

Anyway i have the suspect Intel CEO silence was a sandbagging, he doesn't deny the purchasing.

It could be a great Fab to ramp up in memories production. This is a fact Intel is agan in the memory business and they said officially they will produce the chips in house "if necessary". I believe it will be, 10000 wafers/month are not enough to ship 3D NAND and 3D X-Point chips for upcoming products and customers.

It looks like nobody talks about the $6B project in Israel. This may happen before Fab 42. I wonder what is going on there and why this does not make news!

Seems directly affected by 10 nm delay. Could it repeat fab 42?

The Wikipedia page on 3D XPoint was updated with patents allegedly covering the 3D XPoint device:

Selector: US8148707 (OTS)
Storage: US20090072218 but covered by prior arts US7233054, US20070221905, US20040113137 (PCM containing Sb and Te but not GST)

There seem to be some differences from the press announcement. I am not sure if this will be confirmed or denied by Intel or Micron.

Resistion: The first question, who updated the patent list and why?

There are a couple of eutectics in the Sb-Te phase diagram that have lower melting temperatures than GST. The one at 70%Te has a melting temperature of 544 C, the other at >90% Te has a melting temperature of 422C. Not sure what sort of glass or amorphous structure they have when quenched

If you accept with higher Te concentration the more complete Te bonds will be made and therefore fewer traps and that might result in a higher threshold switching voltage and a higher resistance and thinner films.   (Consider it more like a highly annealed GST material as the starting point). Also one less material to be involved in element separation, from whatever cause.  There are of course many other considerations of performance and characteristics which must be considered, especially the lack of an experience base when changes from GST or doped GST are made.

Get rid of Ge at your peril. Somewhere buried in all the other structure related conduction processe that occur, there is some indication starting to surface that at very localalised level a change in the co-ordination number of Ge may be responsible for swiching and memory.

I don't know who and we might guess why, but assuming we take it as it is, how did they determine it was those PCM patents? Especially the PCM material, as you also doubted.

BTW, this Intel patent application is just a little too PCM-friendly, especially PCMS: https://www.google.com/patents/US20140304475 or https://www.google.com/patents/US20140304475. But these do not mention any materials in particular.

The use of a selector is hard to go along with an MTJ or anything requiring compliance at higher voltages, including correlated electron oxide systems, e.g., http://www.kps.or.kr/home/kor/journal/library/downloadPdf.asp?articleuid=%7B262CBEAF-88E7-4991-8DBA-3437C66C16E4%7D or http://www.nature.com/articles/srep01704/figures/1. So this also tends to favor PCM.

Regarding the case for the selector, I am not sure if possibly manufacturing the ovonic threshold selector would be more economical than a p-n diode. Perhaps that led to the finding of the selector patent.

The PCM if coupled with an OTS selector, needs to have a higher Vth than the OTS, that might explain the finding of the storage material application, although it seems to have already been covered by prior art, which includes GeSbTe with different stoichiometries than 225.