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Max The Magnificent
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re: From RTL to GDSII in Just Six Weeks!
Max The Magnificent   12/4/2010 6:26:08 PM
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I asked your wife and she says "No!"

Mxv
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re: From RTL to GDSII in Just Six Weeks!
Mxv   12/4/2010 3:34:36 AM
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Just curious what the whole project cost from start to finished proto (including the free tools). Wonder if my wife will let me spend our savings...

romat
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re: From RTL to GDSII in Just Six Weeks!
romat   12/3/2010 9:40:53 PM
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Hi James, We all have more than 10 years of experience in chip design and believe me know exactly what does the chip design mean (including custom design, semi-custom and full-synthesis methodologies). Our current flow is really not just about the functional design and does have all of the design phases you mentioned above. We even run the fast spice simulation of the full chip - something that is not that common in the industry (as you probably know). One thing which is probably different in our company is that we really don't try to fight the tools and consider all of the design aspects (synthesis, floorplanning, pnr, etc) as early as at the architecture definition phase of the project. I'll be glad to discuss with you more about our methodologies if you wish - just send us an e-mail "first_name"@adapteva.com Thanks, Roman.

James.Ma
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re: From RTL to GDSII in Just Six Weeks!
James.Ma   12/3/2010 7:13:52 PM
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Is any design not hierarchical ? But once it's synthesized, it's flat. A chip is essentially flat even with floorplanning. ATPG, memory bist, logic bist, boundry IO cell/chain insertion are all flat. And my favorite part, Test Pattern Generation is flat. A big part of chip design is completely orthogonal to the fucntional design. Of course, I've heard of magical scripts that do all of it with one click.

adapteva
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re: From RTL to GDSII in Just Six Weeks!
adapteva   12/3/2010 4:16:36 PM
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Thanks for posting a question on one of my favorite topics, design methodologies:-) The secret to the speed of our design flow (and there really is not secret) is having an extremely hierarchical design flow. We built our architecture and design methodology from day one to be modular and scalable (ie hierarchical). It doesn't work for every design type but it's worked extremely well for our regular architecture. Here are some benchmarks for the Magma tools: -block level synthesis and analysis, 6-9 hrs. The key is to partition the design into small blocks (100k-200k gates at most). Then you farm out these small jobs in parallel. -top level DRC, 30 minutes -top level chip assembly of all the small blocks, 1 hr

adapteva
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re: From RTL to GDSII in Just Six Weeks!
adapteva   12/3/2010 4:08:48 PM
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Sure it's "first-name" @ adapteva.com

da_in1
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re: From RTL to GDSII in Just Six Weeks!
da_in1   12/3/2010 2:49:07 PM
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Not to minimize the achievement, I have a question. I was involved in a similar sized SOC design using Magma tools also. We had benefit of many parallel computers and full SW from Magma. Simply running the design cycle (STA,clock tree insertion, setup/hold fixes, foirmal checks, DRC/LVS, etc) took much longer than 24 hrs of CPU time - even if there were no errors to fix. How could this development be done so quickly with lesser suite of tools and computers (I am guessing that). I guess I am skeptical that these large SOC designs can be done so quickly and error-free .. but maybe we are dealiung with true gurus here .. Just curious.

sreedharsaranga
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re: From RTL to GDSII in Just Six Weeks!
sreedharsaranga   12/3/2010 6:28:11 AM
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Possible and dont mind, Andreas can you leave your mail id.

sreedharsaranga
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re: From RTL to GDSII in Just Six Weeks!
sreedharsaranga   12/3/2010 6:27:10 AM
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Thats the spirit, which will guide and lift to the destination, more over hats of for the self confidence. Really inspiring one for all front end and back end designers, may Andreas stood as role model for all techi guys. Thank you, Sreedhar.

Max The Magnificent
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re: From RTL to GDSII in Just Six Weeks!
Max The Magnificent   12/2/2010 7:52:23 PM
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Re your comment: "All hail the God of design!" You're welcome :-)

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