REGISTER | LOGIN
Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 3   >   >>
ATUL SRIVASTAVA
User Rank
Author
re: Perfecting the 3-D chip
ATUL SRIVASTAVA   10/13/2011 6:32:55 AM
NO RATINGS
This will obviously need new generation of EDA tools too . What is the status on that front ?

Rchandta1
User Rank
Author
re: Perfecting the 3-D chip
Rchandta1   10/13/2011 12:04:26 AM
NO RATINGS
.."volume commercialization of heterogeneous stacks of processor, memory, mixed-signal, networking and I/O chips formed into silicon skyscrapers as high as 100 chips per stack .." - this is very ambitious goal!! Generally sounds reasonable, but very skeptical of the idea of liquid cooling. May fine for special application but definitely not for commercial.

resistion
User Rank
Author
re: Perfecting the 3-D chip
resistion   10/12/2011 6:32:45 PM
NO RATINGS
One also mustn't lose sight of 3d interconnect taking up more and more area especially with more and more stacked dies.

resistion
User Rank
Author
re: Perfecting the 3-D chip
resistion   10/12/2011 6:30:25 PM
NO RATINGS
Hope that can remain an option not become a specific requirement. :)

elctrnx_lyf
User Rank
Author
re: Perfecting the 3-D chip
elctrnx_lyf   10/12/2011 6:19:52 PM
NO RATINGS
will this technology be complete future in the next few years to much higher density processors on a single chip.

JoeData
User Rank
Author
re: Perfecting the 3-D chip
JoeData   10/12/2011 5:49:15 PM
NO RATINGS
Sounds like a perfect use for industrial diamonds - underfill material!

chipmonk0
User Rank
Author
re: Perfecting the 3-D chip
chipmonk0   10/12/2011 5:11:26 PM
NO RATINGS
An excellent overview of current 3D status and roadmap except for the glaring omission of Allvia - a small foundry located right here in Si Valley that has pioneered TSV technology at a prototype level for the last 5-6 years and provides smaller customers access to this technology. They also have Si Interposers with integrated capacitors.

Astronut0
User Rank
Author
re: Perfecting the 3-D chip
Astronut0   10/12/2011 4:19:51 PM
NO RATINGS
hm: You're right! Although 3D itself shouldn't affect lifetime (none of our 3D-ICs from 2004 have failed yet), when more circuitry is added the mean time between failures is likely to become unacceptably small. Continual on-chip testing may be the answer.

_hm
User Rank
Author
re: Perfecting the 3-D chip
_hm   10/11/2011 11:04:10 PM
NO RATINGS
Long term reliability of these parts is also of concern. There has to be new testing methodology.

resistion
User Rank
Author
re: Perfecting the 3-D chip
resistion   10/11/2011 10:48:52 PM
NO RATINGS
The serial nature of stacking and the vertical thermal proximity are fundamental concerns.

<<   <   Page 2 / 3   >   >>


Like Us on Facebook
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Martin Rowe

Test Tool Finds Ethernet Wiring Errors
Martin Rowe
Post a comment
When my house was renovated several years ago, I had the electrician install network outlets in numerous places, then run the LAN cables to a wiring closet. But he didn't document the ends ...

Martin Rowe

Local Electronics Store Supplies Engineers and Hobbyists
Martin Rowe
5 comments
Rochester, N.Y. — Tucked away in this western New York city known for its optics is Goldcrest Electronics, a local store that's supplied businesses and individuals with electronic ...

Martin Rowe

How to Transform a Technology University (Book Review)
Martin Rowe
1 Comment
The Presiding Genius of the Place by Alison Chisolm. WPI, Worcester, Mass., 234 pp., 2016. Engineers love to discuss, and often criticize, engineering education. They often claim ...

Max Maxfield

Aloha from EEWeb
Max Maxfield
Post a comment
Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.