REGISTER | LOGIN
Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
pixies
User Rank
Author
re: Darkhorse litho technologies stay in NGL race
pixies   2/16/2012 3:31:15 PM
NO RATINGS
One thing EUV is good at is creating jobs, high paying jobs for physicists and engineers, for a long time. :)

pinhead1
User Rank
Author
re: Darkhorse litho technologies stay in NGL race
pinhead1   2/16/2012 2:53:40 PM
NO RATINGS
I think the concern is that with the expense of the fancy litho tools, most fabs would only have 1 or 2 initially. Then when you have all of the critical layers needing to go through the tool multiple times, (active, poly, contact, metals and vias) you end up with wafers just queued behind the litho tool all_the_time - because you don't just have 1 lot at a time running in your fab.

double-o-nothing
User Rank
Author
re: Darkhorse litho technologies stay in NGL race
double-o-nothing   2/16/2012 3:44:26 AM
NO RATINGS
Even with DRAM, ~50% layers going from double to triple patterning shouldn't be too bad. Already much better than same 50% already forced to go double patterning.

EnricoHTC
User Rank
Author
re: Darkhorse litho technologies stay in NGL race
EnricoHTC   2/15/2012 1:59:31 PM
NO RATINGS
A healthy mix of technologies will be required. Who will make the masks for Imprint technology or inspect and repair them 1x!! Who will pattern the base structures for directed self assembly, repetitive patterns only?? It might work for memory cells, others? Rapid prototyping and critical layers of the 1xnm and 2xnm nodes, E-Beam dirct write will be the solution.....no masks, easy to change, or simulate process changes, adapt depending on the flow changes across the wafer.. A lot of challenges ahead....smart device integration might be a better way to improve the performance of devices, not just scaling!! Enrico

resistion
User Rank
Author
re: Darkhorse litho technologies stay in NGL race
resistion   2/15/2012 9:13:40 AM
NO RATINGS
If only a small fraction of the chip layers get multiple patterning or double patterning, and most design rules on the SOC are very loose, the extra costs will be diluted. So the "worst case" scenario shouldn't be so bad.

<<   <   Page 2 / 2


Like Us on Facebook
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Martin Rowe

Test Tool Finds Ethernet Wiring Errors
Martin Rowe
Post a comment
When my house was renovated several years ago, I had the electrician install network outlets in numerous places, then run the LAN cables to a wiring closet. But he didn't document the ends ...

Martin Rowe

Local Electronics Store Supplies Engineers and Hobbyists
Martin Rowe
5 comments
Rochester, N.Y. — Tucked away in this western New York city known for its optics is Goldcrest Electronics, a local store that's supplied businesses and individuals with electronic ...

Martin Rowe

How to Transform a Technology University (Book Review)
Martin Rowe
1 Comment
The Presiding Genius of the Place by Alison Chisolm. WPI, Worcester, Mass., 234 pp., 2016. Engineers love to discuss, and often criticize, engineering education. They often claim ...

Max Maxfield

Aloha from EEWeb
Max Maxfield
Post a comment
Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.