"The physical IP we need to create is essentially the same [as for bulk CMOS]." - this can't be true. Layout and DRC rules are bound to be different. Is there any way to automatically transfer the layout data from bulk CMOS to FD SOI? I doubt it
It is kind of same dilemma like DUV immersion. When down to 14nm, both of them will be out of gas. How come foundry would pump in resources for this temporary solution which extend for 2 generations? Besides, SOI wafer capacity(Soitec)and Technology(ST)would be roadblockers for proliferation.
Thank you Kris for your question about design portability.
28nm FD-SOI technology adopts the same design rules as ISDA 28LP HKMG gate-first process, with minor changes and some incremental addition for the FD-SOI specific constructs (like the rules for the hybridation zone, allowing the integration of bulk "hybrid" devices in the FD-SOI technology).
The PDK include scripts for automatic porting of schematics and layouts, easing the porting job.
Of course, digital libraries will need to be re-extracted and recharacterized, while analog blocks will require to be readjusted/ retuned because of the different electrical performances of FD-SOI technology.
Giorgio Cesana, STMicroelectronics
SOI wafers/substrates are significantly more expensive compared to bulk.
On the other hand SOI requires less capex because the wafers are preimplanted requiring less equipment at fab level.
It's a trade off between fix cost versus variable cost.
If you can improve yields very quickly SOI is promising - if not you're wasting very expensive silicon.
It's a trade off and Bohr said they were looking closely at both ... SOI and bulk...and he also did not exclude that some chipmakers might come out with SOI approach...
BTW I spent lots of time in Agrate (when it was still SGS) as well in Grenoble (Thompson) and of course I love Catania -
hey a fab in Sicily -
who can ask for more.
@resistion & Kresearch - FD-SOI scales to 10nm -- see http://www.eetimes.com/electronics-news/4403224/FDSOI-roadmap-renames-20-nm-node-as-14-nm. @Kresearch - wafer capacity is in place -- see http://www.advancedsubstratenews.com/2012/12/the-transition-to-fully-depleted/. @the_floating_gate re: cost/yield -- see Handel Jones showing *major* savings w/FD-SOI (who btw presented at the Common Platform Technology Forum yesterday) http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/
thank you Giorgio...interesting comments about hybridization zone...would you (or STM in general) be interested to describe FD-SOI technology for the upcoming Semiconductor Devices book I am editing? firstname.lastname@example.org
SOI industry talk has been going on for 20 years without commercial success.
AMD dropping SOI due to high cost, design IP, and no chip level advantage
FD-SOI has the same issues
- high cost issue: (single supplier),
- Physical design IP not compatible (ESD ckts, poor high voltage devices, limited and DRC restrictions on multi threashold devices)
@Mrchipguy -- I'd posit that FD does not in fact have the same issues as PD. re: cost - there are 3 wafer suppliers (Soitec, SEH, MEMC). Also suggest Handel Jones' piece cited in my previous comment (he's got FD-SOI die cost = 50 to 60% savings compared to bulk or FinFET). re: physical design -- for ESD etc, because the top Si and insulating layers are so thin, for those devices they just etch back to the bulk (this is the "hybridization zones") -- you can read a full explanation in a white paper by Giorgio Cesana et al from a year ago at http://www.soiconsortium.org/pdf/fullydepletedsoi/planar_fd_silicon_technology_competitive_soc_28nm.pdf. And what they're doing with biasing is awesome.
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I am really curious about this cost comparision model
I don't believe there is no defined cost saving because you compare variable cost (SoC wafers) versus fixed cost due to additional capex required due to using bulk
I am curious about the assumptions in this model
My judgment is different but I I welcome your insight on these issues. On your points
(1) SEH and MEMC have no meaningful FDSOI wafer supply as we speak. They are only on "paper" SOI" suppliers. I think the market data suggest this as AMD still pays extra $500? per SOI wafer after 10 years of production since SEH and MEMC have no SOI capacity. That extra price is a non-starter for mobile market.
(2) Doing "hybridization zones" to solve the ESD and HV devices circuits issues adds process cost and yield issues. Etching off the thin Si and Oxide layer removes the isolation layer, Thus device to device isolation now requires a deep trench to be added back into the process flow into these "hybridization zones". A process nightmare. (My guess is Handel missed this point in his cost study).
Next on hybridization zones since regions were etched off my wafer so by definition my wafer is NOT planar (i.e. not flat) for gate patterning or for entire front-end lithography. Having a not planar front end is another non starter due to lithography tool depth of field and Gate patterning would be very poor leading to poor yield.
Lastly you did not comment on the issues on restrictions on multi -threshold voltages. Looks to me to be yet another non-starter.
FDSOI have been a device options for 10 years. I think these are the reasons.
I can confirm your point is correct and identified by TSMC 5 years ago as a flaw in FDSOI. STI trench is needed (cost) and wafer non-planarity would make "hybridization" 0 yield.
See slide 15 for both points
never mind - I clicked on the wrong link
"IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy."
Intel runs multiple fabs and I am sure they (Intel) have n internal group that studies/develops very detailed cost comparision models.
"The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs."
Do you think 24 to 36 months would apply to Intel?
what would happen to the results of the model in case you plug in a 12 to 18 months for bulk ?
Other major issues is circuit self heating.
This complicates design flow and IP block.
Self heating causes transistor speed and leakage to be different based on past switching history.
This is why Intel is using bulk finfet vs FDSOI or SOI finfet. Why I think Intel dropped FDSOI. Intel solved SOI heat by using bulk so heat all goes to bottom of wafer.
Very smart of Intel.
There is no history effect in FD-SOI. Regarding self-heating, IBM Device Chief Designer Ed Nowak addressed self-heating & SOI (he was talking about FinFET, but cites planar SOI) a few weeks ago. He said, "Self-heating in SOI FinFETs is very similar to that in planar SOI MOSFETs, and as such, the issues and solutions are well understood at a practical product-applications level. For digital circuits, self-heating is not a consideration, as the short-transient energy dissipated from a single transition is absorbed by the heat capacity of the device with a negligible temperature rise. For circuits in which duty factors are sufficiently high, well-established CAD techniques from planar SOI offer solutions. A narrow sliver of silicon connecting a bulk FinFET to the substrate does reduce the degree of self-heating, but similar CAD requirements in product design remain. Other aspects surrounding self-heating include effects on device and interconnect aging, and here again, the techniques practiced over several generations of planar SOI enable design capability to assure the required product reliability in the field."
TSMC had a major program on PDSOI/FDSOI and partnered with freescale during the past decade.
All that work stopped many years ago due to the issues raised.
SOI self heating is perhaps well understood by some but not understood by foundry customers.
Plus even if I accept its well understood (and its not) none of the ~$20B worth of physical IP qualified by the end of 2013 on 28nm took self heating into account so all that would need to be re-designed and re-qualified: correct?
please tell me where I am in error
....Many blocks have high activity factors: correct?
....and after switching....these blocks slow down on FDSOI: correct?
...,.my IP block needs to be redesigned and requalified? correct?
Also, specifically to ST's flavor of ultra-thin body & box (UTBB) FD-SOI, Giorgio Cesana recently wrote: "- The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;
- The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them." http://www.advancedsubstratenews.com/2013/02/sts-cesana-further-explains-fd-soi-biasing-more-in-on-line-discussions-and-linkedin-groups/
thin box 25nm add very very very very very large extra bottom capacitance to each circuit block. Very very very large back gate area. When we switched that at 1 to 2V with any activity factor, power increased for FDSOI with thin box.
I used to work on this and even I have moved on.
Yes, from design side would want to reduce well area and switch small area wells.
That would still leave parasitic C under drain junction (for thin BOX) and that would need to be improved from process side (perhaps make box thinner under drain).
To be clear I do think all this is fundamentally solvable.... I just point this out since I think all these type of work needs to be done if FDSOI ever goes mainstream and FDSOI shows its full potential (low variation and low power). FDSOI is a solid concept (perhaps better than bulk 20SOC or bulk FinFET) but it will take an open debate and a few fixes to move concept forward vs. today.
thanks for the discussion
Here is calculation of very large extra capacitance with your recommended "thin 25nm box" to solve self heating.
Updating what we did 5 years ago and using your thin 25nm BOX recommendation.
Mean n or p-well area size is 100um^2 for a 9 track library at 28nm design (typical for low power design)
For 28nm mean transistor gate oxide is 1.9nm, gate length = 30nm and transistor Width =100nm
Result is (for 25nm BOX) back gate parasitic C is about 2500 times larger than intrinsic gate capacitance for the thin box you recommend
check the math
(100 *1.9)/ (.03*.1 *25.0) = 2533
that is a very very larger extra C to switch (often switched at very large back gate of 1 to 2V ) so that adds a lot of extra power draw.
Pure waist of power without doing useful work and we found block with low activity had higher power in FDSOI with thin box due to this large parasitic C.
So I agree thin box of 25nm helps thermal resistance but that adds too much extra C and removes FDSOI power advantage due to wasted power charging/discharging back gate.
Parasitic C also is on each drain node with this thin of a box as well.
...time to move on from SOI work
I would like to thank Mr. Cesana for pointing out: 6nm is 60A, not 0.6A. Since MR. Cesana’s comments are mostly on UTBB, I will respond to FDUTBB. Remember FD UTBB and FDSOI are not the same.
ST video claims that its UTBB behaves like a vertical double gate. It doesn’t. The double gate is an ideal transistor structure having common gates and common source /drain, thus good control of electrostatics and doubling the transistor on-current, Ion. ST’s UTBB has common source and drain, but has two independent gates consisting of two transistors, the top transistor having the proven HK metal gate very reliable used today in semiconductor industry but the bottom transistor having the Si substrate for a gate and the 25-nm thick buried oxide for gate oxide, sharing 7nm channel is totally new and unproven in reliability, performance, and not adopted by semiconductor industry. During UTBB operation a positive 3V is applied to the bottom gate to control Vt of the top gate. How much the transistor I-on is improved by the positive 3V applied to the bottom gate is not shown. Furthermore, some of channel electrons could drift toward the buried oxide and become trapped inside under the 3V positive bias field during UTBB operation, especially near the source region where electron velocity is very slow. Also, a number of interface states could be generated at the thin Si channel-the buried oxide interfaces, and the channel electron mobility could be degraded due to enhanced scattering at the channel-buried oxide interface, resulting in reduced I-on. These could adversely impact UTBB reliability and performance. These phenomena are unique to FD-UTBB because planer bulk, FinlFET, and FDSOI are not substrate biased or grounded during device operation.
Adele does not seem to admit problem thin box approach.
can you comment on parasitic capacitance from 3V on UTBB (Asele's recommended 25nm thin buried oxide).
It adds too much extra C and wasted power to be viable.
Lastly, the other major issue is strain for high mobility is ineffective in FDSOI.
This limits FDSOI to low performance.
Also has implications on physical IP porting. N/P ratio goes from ~1.3 at 28nm back to ~2. Makes all my physical digital and analog IP non usable without major redesign.
see slide 12 on strain in FDSOI
I first saw ST present on fully-depleted planar SOI technology over 10 years ago -- it's been a long, meticulous journey to reach this point, with a steady stream of papers at the major conferences. The folks at Leti, as well as IBM, ARM, GF, Hitachi, UCBerkeley, Soitec, UCL, Cadence and more have been a major part of this effort, too. This is not a rabbit they've pulled out of a hat. They're getting awesome, silicon-proven results -- especially in terms of cost & power. It looks to me like they've got the right technology at the right time...and now time will tell if they are right.