Analog Devices is not planning on releasing JESD204 IP for FPGA use. Instead, interoperability work is ongoing with FPGA vendors and IP houses to ensure that the available IP works properly with our converters. This allows the designer to select an IP that is optimized for their chosen logic device and application.
Analog Devices offers an FPGA reference design section on the wiki page (wiki.analog.com) including one for a JESD204B Analog to digital converter (AD9250). The AD9250 JESD204B reference design is located at: wiki.analog.com/resources/fpga/xilinx/interposer/ad9250.
This looks like a good, practical overview of the JESD204B standard. Since I'm sure Analog Devices would like this to be as easy as possible for people to adopt, are you planning to release a Verilog or VHDL IP core that engineers can just drop in and connect to FPGA transceivers? The standard seems straightforward but it looks like there's a fair amount of firmware development involved. Just curious, I know there are other manufacturers would probably gain from such an effort on your part.