REGISTER | LOGIN
Breaking News
Comments
Oldest First | Newest First | Threaded View
toom_tabard
User Rank
Author
3D NAND Challenges
toom_tabard   12/3/2013 2:06:34 PM
Great article Gary.

The cost aspects of Samsung/Toshiba's vertical channel 3D NAND approaches were published last month in the IEEE Transactions on Semiconductor Manufacturing (see the following link for free download: http://bit.ly/1imVpBb)

A description of these cost challenges along with other technical issues can be found here at 3DIncites: http://bit.ly/17c1DPw

The main points are:

(1) If those vertical holes and slits are beyond a few tenths of a degree from the normal (in other words, if they are slightly slanted), the whole concept is no longer economically viable and can be undercut in cost by other approaches.

(2) The string currents rapidly decline as densities/capacities increase to the point where the question arises whether such approaches are indeed foundations for several generations to come or are simply one-offs.

Full disclosure - Both the IEEE paper and the 3DIncites piece were written by me.

FraAmelia
User Rank
Author
SS 3D: 24 layers
FraAmelia   12/4/2013 4:23:43 AM
NO RATINGS
Based on what SS discolsed the 128Gb V-NAND has 24 layers not 32. could you please comment?

thanks

etienneazerty
User Rank
Author
Re: 3D NAND Challenges
etienneazerty   12/4/2013 7:57:54 AM
NO RATINGS
Frankly, all the references you gave are based on a etch process that is flawn. Very high aspect ratio etch has no relation with conventional etching, notion like taper angle are inexistent.

With the same number DRAM capacitance scaling is impossible since many generations. Samsung is leader in DRAM by the way, so such etching technology is all but new.

I really think that we need a guy to catch a VNAND die, cut it and show to the community what is really inside so "consultants" can start from real numbers.

resistion
User Rank
Author
Quadruple patterning cheap enough?
resistion   12/7/2013 9:15:19 AM
NO RATINGS
16 nm needs quadruple patterning or 2x double patterning but chips per area not doubled. So patterning cost not doubled? Otherwise stay at 20 nm.



Most Recent Comments
rick merritt
 
Tim R Johnson
 
ewertz
 
antedeluvian
 
ewertz
 
perl_geek
 
R_Colin_Johnson
 
perl_geek
 
R_Colin_Johnson
Most Recent Messages
11/19/2017
3:31:42 PM
Like Us on Facebook
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Martin Rowe

Test Tool Finds Ethernet Wiring Errors
Martin Rowe
Post a comment
When my house was renovated several years ago, I had the electrician install network outlets in numerous places, then run the LAN cables to a wiring closet. But he didn't document the ends ...

Martin Rowe

Local Electronics Store Supplies Engineers and Hobbyists
Martin Rowe
5 comments
Rochester, N.Y. — Tucked away in this western New York city known for its optics is Goldcrest Electronics, a local store that's supplied businesses and individuals with electronic ...

Martin Rowe

How to Transform a Technology University (Book Review)
Martin Rowe
1 Comment
The Presiding Genius of the Place by Alison Chisolm. WPI, Worcester, Mass., 234 pp., 2016. Engineers love to discuss, and often criticize, engineering education. They often claim ...

Max Maxfield

Aloha from EEWeb
Max Maxfield
Post a comment
Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.