The other issue is, as you shrink to new technology nodes and grow the wafer size, the number of die per wafer you get may be more than you can sell. Even if you only run 12 wafers per lot, which is not as economical as running full lots, you may get too many dice for your demand, unless you have a very large die size. This is why it has been more economical for Intel to move to these cutting edge technologies quicker than the rest of the industry since the processor die sizes tend to be larger than the products from the rest of the industry.
I think de geus is measuring "large" by number of designs/number of tool licenses. Considering 180nm is the most popular node for mcu's and probably for analog which have plenty of small designs(just look at the vareity of mcu's).
Yes double/triple litho costs more, but they only do it for a very few layers(out of something like maybe 15-20) and litho is only 25% of total costs according to you're article. How does it become so expensive part of total cost?
@Wilbur: De Geuss said 90nm was never that big because of delays getting it up and running. Not sure why 180nm has been so large but it is in the middle of the field of process nodes still in use today.
The marignal decrease in cost below 28nm is mostly due to double/triple patterning of the mask and the additional complexity in patterning. Going to 450mm wafer is major undertaking and given today's semi environment no company wants to risk money. I think it puts additional pressure on ASML to deliver EUV.
I don't have any data for costs at 16/14nm, but I'm not surprised that the demise of Moore's law is again being brought up. New process nodes are very expensive both in equipment and engineering to get it yielding. Sometimes it is hard to see any reduction of cost for a long time. Going to a larger diameter wafer is even more expensive since almost all of the fab equipment has to be replaced to handle the larger wafer. Again, it takes a lot of engineering effort and time to get the yields up.