While the pcb designer is working on routing and laying out the design, the hardware design engineer also faces the task of reviewing the design in allegro editor sometimes on a daily basis and collaborating with the pcb designer on ideas and solutions on high speed dense designs. Providing an efficient solution described above with timing vision to detect and resolve design rule checks is an excellent benefit for the end users.
A note on designing power distribution networks
After the high speed critical nets are routed, with no other routing complete, the power planes should be routed and corresponding bypass capacitor placement finalized. Then Sigrity can be utilized with an spd linking toolkit that imports the allegro editor design into sigrity power signal integrity toolkit, s parameter models of capacitors can be included, ESL, ESR and capacitor values can also be manually added, circuits selected, settings selected,power nets selected and impedance charts can be created on a specific frequency sweep. Based on these results, modifications can be made to the design. In my experience I have found completing this task earlier in the design process to be more efficient than conducting power integrity simulations towards the end of the design and then trying to modify the stack up to improve results.