Nice bit of sleuthing there, saved me from doing the legwork on nominal operating conditions for my earlier comment.
Given it's a bit of a hypothetical circuit, its unlikely it was intended for an aircraft inverter , possibly for ground testing maybe. But real aircraft inverters run off 28vDC , and would use more elaborate features in the design, specifically targeting reliability and minimising EMI radiation at 200KHz-2MHz (where NDB beacons operate). The parasitic elements in the average 400Hz transformer would potentially resonate in this band so one would expect to see components deliberately placed in there to control EMI.
But otherwise the parts would be reasonable for a 28V inverter (as it needs to be designed to operate at 40v)
One could extend your analysis further by guessing the magnetising current to be about 10% of load current (maybe 30% for an aircraft unit to save weight) maybe 30mH for Lm (via a quick glance at the reactance chart on the wall), Leakage inductance is typically 1% of Lm so Ll= 300uH , Interwinding capacitance , I dunno , probably ~nF (need a similar sized transformer to scale off) . (But generally any cost effective transformer will have parasitic resonances at around 100x operating frequency) so that gets you ~ 1nF.
I leaned towards a biphase reluctance motor myself, because of the conspicuous absence of freewheeling diodes across the MOSFETS which would be needed in a transformer application to carry the magnetising current of a coupled load. A schottky diode would have much lower Vf than relying on the bulk diode in the MOSFET.
Looks like a Jim Williams vintage type design, but I guess if one used a UC2825 or similar to replace all the CMOS parts, a push-pull transformer inverter would be obvious.
Some other observations:
If you replace R33,R34 (1k gate drives) with say 10k resistors, this will slow down the slew rate of Q1,Q2 to the point where the snubbing circuits are no longer needed, (Assuming the transformer was bifilar wound with low leakage, if it was sloppily wound you would still need the zeners but they would get smoking hot.).
The two expensive 250v capacitors could be replaced with normal 50v units by moving them to the other side of R1,R9 , and use 0.1uF to minimise Bom count? The voltage divider could also be incorporated into R6, and save two parts.
Also you don't need two of the AC voltage detector circuits, unless you specifically want to detect a bad connection at the edge connector (the volt-second behaviour of the transformer means the waveforms at the edge connectors are essentially unchanged if one transistor is not switching.)
There is no undervoltage lockout! if the 48v is slowly rising then the +10v rail will sag and the MOSFETS will be underdriven.
C3 is a bit skimpy, with 20ohm tau~50nS , might be OK for 40kHz inverter or a lightly inductive load. As it is the accidental miller clamp of Cgd and R33 will probably carry more current than the snubber. The tau of C3 + R6 is about right to reset at 400Hz, but really need 100x lower impedance if you want to suck up all the leakage energy.
Having the alarm active low is a clever idea, as the alarm will be active when the fuse blows as a result of a short circuit. Having said that I don't think the alarm/protection circuits have been that well thought out . Connecting not_alarm to the 10v rail would probably work as well as anything, giving the most plausible scenarios.
One transistor goes open or its gate is held low (either is unlikely) or the edge connector goes open(likely) , then the remaining transistor now carries double load current, and , and due to the DC in the core the inductance drops to maybe 1/4 of normal , magnetizing current quadruples, so in the more likely case of a faulty connector this magnetising current must circulate in the zener, possibly several amps of reactive current x 110v zener = 200W plus in zener, it will fail short circuit in approx 1sec, and carry maybe 100amps of fault current until it blows apart in another 2secs. At this time the MOSFET has to absorb the energy it might last another 5 seconds until the silicon melts to a blob and it shorts out, another 10 seconds later the main fuse blows and not_alarm drops to 0V.
In the less likely case of one mosfet un-driven, the other struggles along with double load current and quadruple magnetising current, it might valiantly linger on for a few minutes before succumbing to overtemperature, shorting, and blowing the fuse, finally bringing not_alarm low.
A mosfet fails short-circuit , this is the most common failure mode , this will directly blow the main fuse or sometimes the drain bond fuses open, and the gate suddenly jumps to 110v, this might be enough to latch up the 4069, which will then kill the other MOSFET.
an intermittent edge connector or other EMI source can inject a large (negative) voltage spike into the gate driver through the Cdg , as the obligatory 12v gate zener is missing, this spike goes straight into the CD4069, these are old fashioned CMOS, prone to latch-up, which it does and pulls at least one of the outputs high permanently, so killing one or both of Q1,Q2 before the fuse blows,finally bringing not_alarm low.
Anyway , nice puzzle circuit , keep em coming!. Will try not to shred the next one.
Many of these showed up one day, I think the customer was 'bonepiling' them until running low on spares, or simply could not find a place to repair them. Now that we know what they are supposed to do and have a test fixture we can continue to provide this service.
You're right, this was easy in comparison to to some of the unknown boards that sales promises we can handle. ("Can we fix this? I hope so because I just told the customer to send in 20 of them!")
Glad you enjoyed the puzzle. Have a couple more in the works, but as Max says, anyone with a puzzle idea can send it in to him.
My guess is that this part of a system for providing back-up power to the instrumentation on an air-craft from a 48V battery, where it is essential to know WHEN the battery is being drained. This schematic is the power transformer driver.
What is not shown on the schematic is the transformer. EdgeConn1 and EdgeConn2 are permanently connected to the ends of the primary windings of a centre-tapped transformer, and the centre-tap is connected to the 48V battery via a switch. The switch closes (perhaps automatically) if the primary source of power fails.
Normally the circuit can be under continuous operation (so that is can be checked it is working), but the alarm signal only becomes asserted with the load is connected (the primary CT is connected to the battery).
Load Handling Capability: Current: The main MOSFETs are quite hefty (TO-220, 200V, 0.18ohm, 11A continuous drain current at case temp of 100C). They are also quite heavily protected from over voltage (CR8, 110V 5W) and there is a heavy dv/dt snubber (C3 and R5) which is reset by R6 (R6 and C3 has time constant of about 1.4ms, which is about the OFF time of each MOSFET). So I suspect this circuit is intended to drive a substantial load which can be inductive. I'll make the assumption that the MOSFETs are fitted to heatsink, and assume the heatsink is capable of dissipating at least 10W total while limiting temperature rise to about 50C. Assuming MOSFET case temp is at 100C when operating at full power, this causes Rdson to increase by about 1.5, so Rdson=1.5 x 0.18 = 0.27ohms. For 10W total power dissipation, I = Sqrt (10 / 0.27) = 6A max load current per MOSFET at 50% duty.
Voltage: Each MOSFET drain node can only handle 100V max, limited by the clamping zeners. So the loads can be up to 100V if resistive, but if inductive then they are limited to half of this voltage to allow the volt-seconds to balance. The anti-phase drive and the low power rating of clamping zeners suggest that Single-ended inductive loads are not likely; more likely is coupled inductive loads, such as a transformer with a centre-tapped primary, in which case the centre-tap voltage can be up to 55Vdc; note that this node is not on this circuit.
So total power rating is 55V x 6A, let's call it about 300VA.
Both frequency and duty-cycle are fixed (there seems to be no form of feedback to modulate either of these) so there is no intention to regulate the final output at the load.
Typically in a push-pull converter the secondary is rectified and filtered to produce a DC voltage. What is neat about this circuit is that the output voltage is sensed on the primary side by the filtered peak detectors and used to assert the overload ALARM signal when the output voltage drops a certain level caused by a heavy load.
I imagine one could next use the ALARM signal to trigger a pulse generator that resets the flip flops for some time creating some cooling off period (i.e. hiccup mode) or just latch the signal requiring a system reset or power cycle to recover.
@David What is on the secondary side of the transformer?
Don't know. All I know is one of our sales people promised a customer that we could repair absolutely anything and the boards showed up - no chassis, no backplane, no transformer, no information other than they were from some piece of legacy telecom power supply. We made a test fixture once we understood what these boards are supposed to do.
Was tempted to jump into the discussion but didn't want to spill any cool beans too soon. It was great to see how everyone went through similar thought processes based on the little bits of information gleaned from the schematic.
Glad you like puzzles like this, have another one in the works. But as Max said, anyone with puzzles of their own can send them to him.
@Glen...well I got most of that right - centre tap transformer, non-overlapping FET drive, alarm on either output not going high enough, etc. Glad I am not tooo stupid yet. But you have not told us exactly what this circuit is for? What is on the secondary side of the transformer?
And thanks for that - I love stuff like this. Any more of them will be very welcome.