there is a lot of research going on about design emulation on off-the-shelf multi-GPU systems, such as the one from NVIDIA. I think with a proper handling of timing critical interfaces with virtual peripherals on multiprocessor systems, that there is a lot of potential in it. Still exiting times ahead.
thank you for commenting and for the hint. My understanding is that GPU-based verification engines belong to the acceleration class of machines, with speedup factors of less than one order of magnitude (less than 10X) versus HDL simulators. Hardware emulators run several orders of magnitude faster than HDL simulators.
If you wish we can have a discussion one-on-one. My email is "firstname.lastname@example.org"