Scott, I asked POET what they thought about your long comment and got an even longer answer:
POET Technology is revolutionary in that it is the first – and to our knowledge, only – technology to integrate electrical devices used in large scale ICs today in native III-V. For high speed digital logic, they are both pHFET and nHFET (enabling static CMOS digital circuit topology), both pHBT and nHBT for analog and mixed signal circuits and an optical thyristor to fabricate optical devices. The structures are compatible with scaling to nanometer scale by leveraging processes and lithography capabilities already proven in Si CMOS. We are expecting a minimum of 5X higher mobility of carriers in these devices when compared to native Si devices. The technology is also capable of integrating optical and electro-optical devices which bring optical signaling and signal processing to the same component.
To address some of the readers' comments regarding performance, density and cost:
- For high speed digital logic implemented using the nHFET and pHFET transistors. Comparing POET to Silicon CMOS for digital SoCs, logic performance will be 4 nodes better in power AND 3 nodes better in speed. We expect comparable if not better density as we expect to require far less buffering and upsizing of logic cells.
- For analog and mixed signal circuits. In addition to p and n HFET's higher transconductance, lower noise figure and larger linear operating range, we also have nHBT and pHBT devices with effectively zero minority carrier storage, very high gains and very fast transit times. Mixed signal performance will be better due to lower on chip switching noise, and better digital to analog isolation due to the semi insulating substrate, and the circuits in general will be smaller due to higher drive per unit size. We expect to support serial I/O at 50Gbps if not 100Gbps.
- Lastly are the optical capabilities of the POET process where our customers will have the ability to have optical I/Os on their devices along with digital and/or analog circuitry described above. We expect on chip memory to be denser and faster due to thyristor based 2-element memory cell and much better sense amplifiers.
All of the capabilities described above will allow designers of complex systems and SoC solutions to innovate in ways that have not been possible to date with existing processes. These system integration possibilities will enable lower solutions and manufacturing costs.
Looking at IC costs, one needs to consider the total cost of ownership viewpoint in making comparisons. If you look at cost/sq mm of state of the art CMOS, these numbers generally assume high fab utilization and do not amortize the cost of R&D, including NREs. The number of companies that can develop the process and manufacturing capability for state of the art CMOS can now be counted on one hand, and that is because there are only a handful of customers or vertically integrated companies that have applications where the volumes can absorb the development costs and fill the fabs. With respect to 40nm and manufacturing technology, our FEOL process is substantially simpler than an equivalent CMOS technology, and our BEOL is the same. With adoption and resultant volume scaling, we expect that the wafer costs will come down thanks to volume and manufacturing is within the capability of 4 to 6 year old toolsets. NRE costs will be significantly lower as compared to like performance silicon nodes, drastically lowering the breakeven point on a unit basis. Users of this technology will address applications that differentiate on performance capabilities or differentiate on cost due to system level partitioning and optical integration not even possible with existing technologies, and will be able to command differentiated product pricing. Bottom line is that a whole new set of business cases become possible with this technology that were previously impossible due to inaccessibility of required performance.
In summary, POET technology will not replace, but supplement CMOS in applications requiring the highest performance, integration and/or lowest power. Our vision is that many foundries will eventually offer POET Technologies processes along side of their existing processes to their existing customer base to enable solutions that are not realizable today with any other process out there.
POET is mum on the details, but claims to be capable of 8" wafers, and says there is a company they signed NDA with which can fab 4 - 8 inch wafers in the same chamber. However, most others making III-V transistor channels are trying to put them on Si wafer with special buffer layers to handle the lattice mismatch.
GaAs was to replace Si in digital ASICs 30 years ago. It never happened.
Can GaAs use Si 300mm manufacturing infrastructure?
I thought that GaAs is made in ultra-specialized 6" fabs - has anything changed and why?
I agree with you . When I started my professionnal life on GaAs and its relative other III-V compounds in the 80's , people were already saying that GaAs was , is and will always be the material of the future. This was 30 years ago. It will take more than nice hearing acronyms (POET or PET) to beat Silicon.
I am not saying though that in some opto-electronic applications , GaAs and its family cannot bring something : it is already the case for some lasers or some analog circuitry (besides the SiGe HBT technology from IBM , for instance)
Alex - yes, I do. One of the unparallel advantages of monolithic 3D is the ability to mix and match - heterogeneous integration. GaAs as it currently available is already $1B business as was recently reported. If its true that these techniques would make it better than GaAs has value for some application. Monolithic 3D allow us to integrate a wafer been processed at GaAS line by bonding it to a silicon wafer providing the ability to leverage the best of both technology for a better system. A better product should win and someone will move forward to build it.
The "big guys" are expected to explore all possibilities, and its true on 1 our of 100 of these projects pan out--for instance finFETs are a perfect example. A long-shot that has paid off big, making it worth also investigating the 99 that failed.
This comment doesn't make sense: "Silicon digital logic hits the wall at 4 GHz, but we can produce small gallium arsenide [GaAs] analog circuits switching at 100 GHz today and 400 GHz in the not too distant future,"
The only part of silicon that hits a "wall at 4GHz" is power. Huge 500nm silicon devices have had ft,fmax of 5GHz or more for 20 years. Today, silicon is at sub-20nm. Planar silicon MOSFETs are knocking on the door of 1THZ with a T for Tera.
The silicon world (read: Intel) just stopped focusing on ft because of power limits and now focus on density with multi-core computing using finfets (lower ft than planar). For non-scientific applications, technology is not about logic circuit speed much anymore.
Furthermore to compare the speed of an analog circuit to a digital circuit is misleading. Analog is always faster for the same technology because the circuit can perform useful functions (i.e. gain) closer to the device ft regardless of the technology.
If one wants to compare two technologies the conversation needs to factor in power, area, speed, and cost of like circuits. The study between Si and GaAs has been on going for at least 50 years now and silicon is still on top. And it is on top because the technology world makes decisions based upon all four parameters collectively whereas NASA, DOD, ESA, CERN, and other low volume, scientific-centric enterprises don't care much about cost.
The 1980's mantra that "GaAs is the silicon of the future. It is and always will be." seems to still apply. Engineers just can't get their minds past the potentially available 3x improvement factor in speed; cost be damned.
In many respects the arguments in this article are similar to the arguments made during the FPGA wars. Actel and Quicklogic with their lower power technology could never get ahead of the SRAM based approaches of Xilinx and Altera. This was because the purported inferior SRAM approaches were always at least one technology node ahead. A similar claim made in this article.
When I see GaAs competing on a cost-speed-power-size basis, I will rethink my position.
"Those who fail to study history are doomed to repeat it."