Okay. But a fin does not have a variable fin width. It's been at 8nm for both 22nm and 14nm.
Intel has shown a graph at IDF that they expect power ocnsumption at 10nm to come down much more than historically. That just shows how variable these things are, although the combined performance+power improvements are pretty consistent accross the nodes.
I am not talking about Dennard's prescription of what ion implant dose is needed or how all dimensions and operating voltage has to scale. At the heart of those equation is physics law that both current and capacitance scale with linear scaling if everything else is kept same; that is performance is CV/I and active power is I.V. Going node to node the total transistor width scales by 30% if currennt density (A/um the way reported in IEDM) stays constant and so does the total cap assuming that metal thickness scales at the same rate that metal spacing scales. Yes, not everything scales at the same rate and that's where innovations come e.g. with Cu metal/low-k. A better transistor (e.g. FinFET, adding high-k, adding strain, etc) is expected to do a better than 30% per node.
Gate capacitance has not been the major contributor to the total capacitance for over a decade. So the fact that Lg did or did not scale does not change total capaictance. Drive current is also not a strong function of Lg once you get to velcoity saturation or source side injection (whether ballistic or non ballistic) whichever model you favor.
Quantum effects were playing a rule for a long time. even at 90nm with the physical oxide thickness of 1.2nm, you have a 0.3-0.4nm adder due to quantum effects.
Says quantum mechanics. Says the fact that transistor scaling hasn't been Dennard-like for well over a decande. Says the fact that certain important features of the transistor, like Lgate and especially the dielectric insulator, have stopped scaling in the last decade. Says the fact that a transistor isn't a Dennard-transistor anymore but a 3D finFET. Says the fact that Dennard scaling completely ignores the interconnect.
Moore's Law is an economic law and has nothing to do with Dennard scaling.
So I repeat: a modern quantum mechanical transistor is much, much too complicated to be approximated by the classical Dennard model.
Says who? This is simple geometry scaling. Traditional Dennard's scaling also required scaling of Vdd at the same pace. I see that part getting a hit because of Vt not scaling as fast. If scaling does not translate into expected power reduction (Dennard's rule) and cost per transistor reduction (Moore's law) there is absolutely no point in doing it
The 65% SRAM power reduction over two nodes might come along or even better than expected Dennard's rule. But SRAM bitcell is not limited by metal pitch so doesn't get a hit from metal-metal cap increase.