Personally, I'll be interested in the design constraints of having a 4Gsps ADC share space with a 1000+ pin FPGA. RF noise factors, isolation, number of PCB layers, etc. All the low-noise designs I've looked at have a separate [sometimes even shielded] RF section for good reason.
I look forward to seeing a development board based on this chip.
You are absolutley spot on, well you wrote the white paper so you should be :) this means the RF engineer can get more involved at the system level not just the traditional RF design. Of course this also opens up new areas for them to optimise and trade performance to deliver a platform which meets the requirements placed on them. They are after all the people we discuss these aspects with to make these tradeoffs.
Hi Adam, Good observations. I got a message from an RF engineer on LinkedIn soon after this announcement wondering if he was out of a job. Of course not...if anything the tool chain and higher levels of abstraction will allow the RF team to hand over a more complete subsystem for easier integration by the rest of the digital design team. As you point out the tools will be critical and should also allow non FPGA designers who have the relevant systems or application knowledge to more easily capture that in the subsystem design. And yes...take some of that clocking pain away as well.