On your p. 2 figure, the two cases on the right for 36 and 38 nm pitch show different distributions of illumination points in the dark circle, and these are different still from 32 nm and (more extremely) 26 nm (the placement there also looks incorrect, for horizontal lines). These distributions came about through source-mask optimization (SMO). My understanding now is that EUV patterns shift when the wafer topography is higher or lower, and this is quite sensitive to pitch.
resistion wrote that the silicon lattice constant is 0.54 nm. As feature sizes shrink, the analog idea of patterning onto continuous silicon breaks down. Instead, we are talking about a digital pixellated lattice of individual atoms, and the patterning process will be addressing individual atoms.
The silicon lattice constant is 0.54 nm. This already makes 10% CD control impossible for 10-11 nm features, and so at ~20 nm CD it is already very difficult. IMEC projecting further into an era of nonsense fueled by EUV and nanowires.