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Open Source Core Advances

By   07.13.2015 0

In late June, Berkeley held a workshop to get to know what research has been underway on RISC-V. RISC-V is an open instruction set architecture (ISA) originally developed at Berkeley and based on established reduced instruction set computing principles. It is a minimal, modular ISA ready for hardware implementation, freely available to both academia and industry.

The workshop was sold out with 120 attendees representing 30 companies and 20 universities. The Berkeley speakers were in the minority, with other speakers from Australia, England, India, Italy and Switzerland.

It appears RISC-V is experiencing a bandwagon effect. Conversations in the hallways suggested multiple commercial efforts may be underway. The speculation was primarily due to the very active participation from the commercial engineering community.

The program covered past work and achievements and put even more emphasis on future challenges and research directions to pursue. Motivating talks covering multiple areas are fundamental to any successful systems workshop and particularly one of this type.

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Three of the first-day’s presentations gave proposals on compressed and vector extensions as well as on a class of architecture that my colleagues termed privileged. Krste Asanovic, Dave Patterson, and Berkeley colleagues outlined a number of goals and rationales behind RISC-V compressed (RVC), as well as proposed a number of new extended RVC instructions.

It is an open question whether the current draft set of those instructions will be sufficient to cover all possible future scenarios or if more RVC instructions will be needed as systems evolve. In addition, further work likely will be needed to figure out not only the relative values of the instructions but also whether those values change as 32- and 64-bit systems evolve. Nevertheless, the initial data shows RISC-V has the smaller code size than x86 and ARM.

In regard to a privileged architectural class, virtualization (in time, memory, and etc.) permeates all levels of the ISA. The architecture offers a set of modular and clearly delineated levels of software for applications, hypervisors and the operating systems. The architecture lends itself to simplicity at the embedded systems level, to size/scale at the virtual/memory management level, and to low implementation cost. 

Also on the first day, colleagues at the University of Cambridge presented their lowRISC architecture. One of their goals is to bring the benefits of open source software to silicon by producing a complete open-source reference system-on-chip design for others to build on.

Presenters described other specific chip design efforts on the second day of the workshop. Z-scale is a tiny RISC-V 32-bit core generator for microcontrollers and embedded systems, similar to ARM Cortex M0/M0+/M4, integrating AHB-Lite interconnects. Z-scale shows advantages over ARM Cortex-M0 architecture in performance, area efficiency, frequency, voltage and dynamic power.

Open source implementations of Z-scale at Berkeley are available in Verilog and Chisel which is a hardware-device-language embedded in Scala. Going forward, the core generator will be integrated as a component of the Rocket chip generator.

The Berkeley Out-of-Order Machine (BOOM) is a work-in-progress. Essentially, it is a RISC-V RV64G-based out-of-order superscalar application core with higher performance, much better area efficiency, and comparable frequency-wise to the ARM Cortex-A9.

Raven3 is a 28nm RISC-V vector processor with on-chip DC/DC convertors. Maximizing energy efficiency is the main goal of this architectural paradigm. More details on all of these RISC-V designs are available online.

— Saleh Elmohamed is a senior researcher and educator on leave from Cornell and currently at Berkeley closely collaborating with the ASPIRE Lab on energy modeling and simulation of RISC-V based architectures.

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rick merritt   2015-07-13 10:25:26

If anyone is doing a commercial SoC design with RISC-V, I'd like to hear about it.

masaleh   2015-07-14 17:42:31

Hi Rick,

Maybe Mullins and his team at Cambridge would have some more info on that.

 

maronson22   2015-07-23 20:25:13

Hi Rick,

  Here at Rumble Development Corp.,  we have had a great experience working with RISC-V.  We have developed a small, fast RISC-V core for an FPGA.  We have already provided a complete camera solution for use in a dental camera,  and are currently devloping our next generation of timelapse cameras based upon this technology (shipping by end of year).  A video processing SOC is also in the works.

  In the past, we have spent many engineering cycles learning new tools and architectures in order to design the most effective solution for each of our products. RISC-V provides us with a common platform we can use for all our future designs, from simple IOT sensors to hundred-megapixel, multi-sensor cameras.  While we are using our own RISC-V compatible core for the lower-end products, the RISC-V community provides us access to high-end processor designs we could not possibly create ourselves. 

 

Mike Aronson, President

Rumble Development Corp.

 

rdm34   2015-07-24 07:32:14

Hi Rick,

I believe there is already a RISC-V based product shipping (a camera I believe). We are working with two startups that are planning to use RISC-V cores and the lowRISC SoC and also chatting to a few other established companies, large and small. There are also RISC-V based projects at a number of larger companies in the US and elsewhere, e.g. at Oracle http://riscv.org/workshop-jun2015/riscv-cava-workshop-june2015.pdf


Rob Mullins, Uni. of Cambridge/lowRISC

 

masaleh   2015-07-29 19:03:00

Hi Mike,

Many thanks for the info about RDC RISC-V based products.

My colleagues and I would really love to hear more of your

thoughts on that as well as on the SoC design you pointed

out to. I gather that is still work in progress. 

-Saleh

 

 

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