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Profile for Mark L Torrey
Mark L Torrey
Member Since: November 28, 2012
Author
Posts: 45
Providing the full arena of IC Layout Consulting services for over 40 years, including digital and mixed signal / analog technologies and product lines. Expert level in Cadence, Mentor and Synopsys Layout Tool Suites. Proven track record in all areas of expertise including Full Chip Floorplanning; Full and Semi-Custom Layout; APR Cell, Macro, Block and Full Chip Layout; Physical Verification, DRC, ERC, LVS; Chip Assembly, Integration and Physical Verification; Scripting and Programming, CAD and Methodology Development specifically for Layout and Physical Design arenas.


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Aloha from EEWeb
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Just a few minutes ago as I pen these words, I posted this blog about this month's Cartoon Punchline Competition over on EEWeb.com.