TSMC Preps 10nm, Tunes 16nm

SANTA CLARA, Calif. — TSMC will start early production on a 10nm process this year and 7nm in 2017, executives said in a road map update here. In between, the foundry giant will release a cost-reduced version of its 16nm process next year and a broad portfolio of specialty processes for the Internet of Things, automotive and sensors.

The road map suggests TSMC could leapfrog Intel to producing 10nm chips, although naming conventions for nodes these days hide the underlying details of the processes. What’s more clear is TSMC has gotten off to a slow start with its 16nm FinFET process with close partners such as Xilinx saying they have taped out but not yet shipped their first chip in the process. Xilinx also plans to skip TSMC’s 10mn process in favor of its 7nm node, a significant choice given Xilinx typically acts as a logic driver for new TSMC nodes.

In addition, TSMC announced plans for specialty RRAM and MRAM memories that would act as alternatives to embedded flash. It also gave an update on its integrated fan-out (InFO) process, a low cost chip stacking technology that will be in production in 2016 and reportedly will be used in Apple’s next-generation handset, the iPhone 7.

“If anyone will push Moore’s Law to the furthest extent, it will be TSMC,” said Jack Sun, vice president of R&D and chief technologist, speaking at a partner event here.

Sun and colleagues showed a stack of slides about TSMC’s road map but would not provide them to the press or allow photography in the session, attended by several hundred partners and customers. Likewise it would not allow photos of a 10nm FinFET wafer or an InFO wafer with stacked 15mm² DRAM it showed in a booth on its exhibit floor.

The 10nm ramp “is clearly for a new phone and the candidate is clear,” said Handel Jones, principal of consulting firm IBS, Inc. (Los Gatos).

Mike Demler, an analyst with the Linley Group, attended the event and provided his perspective:

Although the nominal gap in process nodes between Intel and TSMC appears to be narrowing, TSMC is not likely to catch up in terms of actual Moore’s Law scaling any time soon. TSMC’s 16FF+ process delivers only 20nm scaling, so they are still a generation behind Intel’s 14nm in terms of actual die area. TSMC said that 10nm shrinks by 0.52x from 16nm, nearly identical to the 0.53x scaling that Intel achieved from 22nm to 14nm. So if they stay on schedule, in 2017 TSMC will be in production on a 10nm process that is equivalent to the 14nm technology that Intel began producing in 2Q15. At that rate, even though Intel has slipped 10nm to 2H17, they will remain at least a year ahead of TSMC.

TSMC made a working test chip in its 10nm FinFET process, said Sun. The process should deliver a 0.52x area scaling compared to 20nm and support either 18% higher speeds or 40% less power than TSMC’s current leading-edge 16FF+.

The bad news is the 10nm process requires triple patterning and an entire new EDA design flow, said Rahul Deokar, a product management director from Cadence in a separate talk. “There’s an explosion in physical design rules by an order of magnitude,” he said.

The use of colors to delineate separate lithography passes was an option at 20nm, the first node to use two passes through stepers for some layers. At 10nm the use of colors becomes mandatory not only in routing but in placement and extraction tasks as well, he said. Overall, the 10nm process delivers a 10-20% boost in power, performance and area, Deokar said, but was not more specific.

Cliff Hou, vice president for design technology at TSMC was more conservative. He estimated engineers working in the 10nm node will face more than 5,000 design rules compared to 4,000 at 16nm and less than 2,000 in the 28nm node.

TSMC has finished 8,000 standard cell designs in 10nm. It has also validated 10nm minimum voltages in all compilers and voltage ranges from 0.4 to 1.3V. A 56 Gbit/second serdes block should run on 22% less power in 10 than in 16FF+ node, he added.

Next page: 7nm in 2017, lower cost 16nm next year