MADISON, Wis. — Is the semiconductor industry prepared to profit from the emerging 4K UHDTV market? If so, how ready is anyone?
As soon as consumers start looking for 4K Ultra HDTV (assuming they do), the indispensable element in the next-generation set-top box is a decoder chip capable of handling all the highly compressed video streams.
Compression will be carried out by using a complex but flexible “toolkit” developed by the High Efficiency Video Coding (HEVC) standard, a successor to H.264/MPEG-4 AVC (Advanced Video Coding).
Leading video chip companies such as Samsung, Broadcom, and ViXS Systems are all said to have developed their own HEVC chips. But these devices are still in early versions.
The nightmare secretly anticipated by many chip designers is the long and arduous task of verifying whether a video chip is truly capable of decoding every HEVC-encoded video stream.
HEVC, also known as H.265, is said to halve the bandwidth requirement for video, thus enabling migration to 4K video.
The issue is that there are so many variable options embedded in the standard's toolkit. Each encoder designer is free to use any tricks available in the toolkit to wring the best compression performance out of the standard.
That flexibility, however, poses a huge headache for decoder chip designers, since they need to make sure that their chip “understands” all the variables present in different HEVC-compressed video streams, explained Alan Scott, CEO of Argon Design.
HEVC in multi-core chips
To complicate the matter further, in HEVC, multi-core chips can encode streams in independent tiles, while hardware implementations may choose to minimize cache sizes by using wavefront encoding. However, decoders need to support all options.
Also, “HEVC has moved from a fixed partitioning scheme to a quad-tree decomposition scheme. This means there are orders of magnitude more variations of block sizes for coding/transform/prediction,” Scott told me.
If you've lived long enough to remember when MPEG-1 and MPEG-2 standards were developed (in the 1990s), you also probably remember a test sequence video stream showing tulip fields against Dutch windmills on a screen. The video clip showed a beautiful landscape panned slowly. But pretty soon, you might have wearied of tulip fields. You might have seen tulips in your dreams.
In those days, you could validate your video decoders by looking at the screen, says Scott. But that visual practice won't cut it anymore, he believes, because “HEVC is many times more complex than MPEG-2.”
He notes that the new standard “has so many options, variables and settings. It's hard to cope with all that complexity.”
Four-year-old startup Argon Design, whose lead engineers came from the UK-based chip company AlphaMosaic, has created what the company calls “the industry's first comprehensive validation suite for the HEVC specification.” The first version of the company-designed evaluation suite will become available at the end of this month.
The 15-person company has produced a suite of HEVC bit streams that test and verify the complete space of valid HEVC bit streams. “Because we are coming from a chip-design background, we created this from the user point of views,” Scott said.
The team created a pseudo code — “sort of a mix of English and mathematical description,” according to Scott — out of the HEVC spec.
They wrote a compiler for the HEVC specification that directly understands the pseudo-code and equations contained in the HEVC spec.
By creating a mathematical model of the entire coding process, Argon Design produced a comprehensive set of HEVC-encoded bit streams. The team also created a tool that details exactly which sections of the spec are covered by any set, or subset, of a bit stream.
The resulting coverage report is cross-linked to an interactive version of the HEVC specification that highlights exactly which sections and equations are being verified, the company explained. The tool, in turn, will help chip designers to find incompatibility between a decoder and an encoder, said Scott.
Competitive landscape
When asked about the company's track record for tool development, Scott said that his company started out as a technology consultancy.
Apart from Argon Blaster, a tool developed to verify 10 Gbit/s network equipment based on the Netronome Flow Processor, Argon Design's newest product is the HEVC validation suite the company announced this week.
Argon Design has been using Argon Streams and Argon Coverage Tool to verify the HEVC reference decoder developed by the standards body. “This process has already resulted in over 40 issues with the HEVC specification and reference decoder implementation being reported back to the standards body,” Scott said.
There's an incumbent company, Allegro VDT, located near Grenoble, France, experienced in producing compliance bit streams designed for intensive testing of H.264/AVC/MVC/SVC decoder implementations.
Along with Allegro, Sarnoff also offers tools for HEVC. But both Allegro and Sarnoff offer syntax streams, “based on the own encoder implementations rather than being derived directly from the specification,” according to Argon Design.
The French company showed off earlier this year its HEVC/H.265 Hardware Decoding IP, billed as “the world first HEVC/H.265 hardware decoder IP” based on an unprecedented multi-core architecture.
Meanwhile, IP companies have also begun offering HEVC solutions.
Imagination Technologies last month announced a new PowerVR video decoder for HEVC. The PowerVR D5500 is a multi-standard, multi-stream video decoder with a multi-core architecture, “allowing performance to be easily scaled for high resolution or high frame rate applications up to full HEVC level 5.0,” claims Imagination. Describing it capable of enabling “4K resolution content to be decoded up to H.265 L5.0 4Kx2K @ 60fps,” the UK company says the new PowerVR D5500 video decoder is available now for licensing.
The competitive landscape for HEVC chips is now compelling Argo Design to roll out its own verification suite on the commercial HEVC market.
When I was interviewing Argon Design, two things popped up.
The company explained:
...In HEVC, multi-core chips can encode streams in independent tiles, while hardware implementations may choose to minimize cache sizes by using wavefront encoding. However, decoders need to support all options.
...HEVC has moved from a fixed partitioning scheme to a quad-tree decomposition scheme. This means there are orders of magnitude more variations of block sizes for coding/transform/prediction.
Now both of these things pointed out above tells me that yes, verifying your decoder against your own encoder may work, but certainly it doesn't guranatee that your decoder can support various encoders that will soon be out there! That sure sounds like "unintended consquences" waiting to happen.